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Added support for memories to flatten (techmap)

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This commit is contained in:
Clifford Wolf 2015-01-17 20:46:52 +01:00
parent 7031231145
commit 8658eed52a
1 changed files with 22 additions and 3 deletions
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25
passes/techmap/techmap.cc
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@ -153,9 +153,6 @@ struct TechmapWorker
void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl) void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl)
{ {
if (tpl->memories.size() != 0)
log_error("Technology map yielded memories -> this is not supported.\n");
if (tpl->processes.size() != 0) { if (tpl->processes.size() != 0) {
log("Technology map yielded processes:\n"); log("Technology map yielded processes:\n");
for (auto &it : tpl->processes) for (auto &it : tpl->processes)
@ -176,6 +173,22 @@ struct TechmapWorker
break; break;
} }
dict<IdString, IdString> memory_renames;
for (auto &it : tpl->memories) {
std::string m_name = it.first.str();
apply_prefix(cell->name.str(), m_name);
RTLIL::Memory *m = new RTLIL::Memory;
m->name = m_name;
m->width = it.second->width;
m->start_offset = it.second->start_offset;
m->size = it.second->size;
m->attributes = it.second->attributes;
module->memories[m->name] = m;
memory_renames[it.first] = m->name;
design->select(module, m);
}
std::map<RTLIL::IdString, RTLIL::IdString> positional_ports; std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
for (auto &it : tpl->wires_) { for (auto &it : tpl->wires_) {
@ -252,6 +265,12 @@ struct TechmapWorker
apply_prefix(cell->name.str(), it2.second, module); apply_prefix(cell->name.str(), it2.second, module);
port_signal_map.apply(it2.second); port_signal_map.apply(it2.second);
} }
if (c->type == "$memrd" || c->type == "$memwr") {
IdString memid = c->getParam("\\MEMID").decode_string();
log_assert(memory_renames.count(memid));
c->setParam("\\MEMID", Const(memory_renames[memid].str()));
}
} }
for (auto &it : tpl->connections()) { for (auto &it : tpl->connections()) {