Added support for bufif0/bufif1 primitives

frontends/ast/simplify.cc

@@ -498,6 +498,31 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage)
 		}
 		children.clear();
 
+		if (str == "bufif0" || str == "bufif1")
+		{
+			if (children_list.size() != 3)
+				log_error("Invalid number of arguments for primitive `%s' at %s:%d!\n",
+						str.c_str(), filename.c_str(), linenum);
+
+			std::vector<RTLIL::State> z_const(1, RTLIL::State::Sz);
+
+			AstNode *node = new AstNode(AST_TERNARY, children_list.at(2));
+			if (str == "bufif0") {
+				node->children.push_back(AstNode::mkconst_bits(z_const, false));
+				node->children.push_back(children_list.at(1));
+			} else {
+				node->children.push_back(children_list.at(1));
+				node->children.push_back(AstNode::mkconst_bits(z_const, false));
+			}
+
+			str.clear();
+			type = AST_ASSIGN;
+			children.push_back(children_list.at(0));
+			children.push_back(node);
+			did_something = true;
+		}
+		else
+		{
 			AstNodeType op_type = AST_NONE;
 			bool invert_results = false;
 
@@ -532,6 +557,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage)
 			children.push_back(node);
 			did_something = true;
 		}
+	}
 
 	// replace dynamic ranges in left-hand side expressions (e.g. "foo[bar] <= 1'b1;") with
 	// a big case block that selects the correct single-bit assignment.

frontends/verilog/lexer.l

@@ -169,7 +169,7 @@ namespace VERILOG_FRONTEND {
 }
 <STRING>.	{ yymore(); }
 
-and|nand|or|nor|xor|xnor|not|buf {
+and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1 {
 	frontend_verilog_yylval.string = new std::string(yytext);
 	return TOK_PRIMITIVE;
 }