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Added $lut support in test_cell, techmap, satgen

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This commit is contained in:
Clifford Wolf 2014-08-31 17:06:36 +02:00
parent 2a1b08aeb3
commit 8649b57b6f
4 changed files with 102 additions and 9 deletions
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10
kernel/rtlil.cc
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@ -1768,8 +1768,7 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
return;
if (type == "$mux" || type == "$pmux")
{
if (type == "$mux" || type == "$pmux") {
parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
if (type == "$pmux")
parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]);
@ -1777,7 +1776,12 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
return;
}
bool signedness_ab = type != "$slice" && type != "$concat";
if (type == "$lut") {
parameters["\\WIDTH"] = SIZE(connections_["\\A"]);
return;
}
bool signedness_ab = !type.in("$slice", "$concat");
if (connections_.count("\\A")) {
if (signedness_ab) {