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ABC9: Cell Port Bug Patch (#3670)

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* ABC9: RAMB36E1 Bug Patch

* Add simplified testcase

* Also fix xaiger writer for under-width output ports

* Remove old testcase

* Missing top-level input port

* Fix tabs

---------

Co-authored-by: Eddie Hung <eddie@fpgeh.com>
This commit is contained in:
Benjamin Barzen 2023-04-23 01:24:36 +02:00 • committed by GitHub
parent 7efc50367e
commit 8611429237
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GPG key ID: 4AEE18F83AFDEB23
4 changed files with 26 additions and 2 deletions
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6
passes/techmap/abc9_ops.cc
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@ -674,8 +674,12 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
continue;
auto offset = i.first.offset;
auto O = module->addWire(NEW_ID);
if (!cell->hasPort(i.first.name))
continue;
auto rhs = cell->getPort(i.first.name);
if (offset >= rhs.size())
continue;
auto O = module->addWire(NEW_ID);
#ifndef NDEBUG
if (ys_debug(1)) {