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fix assignment of non-wires

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This commit is contained in:
Stefan Biereigel 2019-05-23 17:55:56 +02:00
parent c2caf85f7c
commit 85de9d26c1
1 changed files with 19 additions and 16 deletions
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7
frontends/ast/genrtlil.cc
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@ -1500,8 +1500,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
for (int i = 0; i < GetSize(left); i++) for (int i = 0; i < GetSize(left); i++)
if (left[i].wire) { if (left[i].wire) {
std::map<RTLIL::SigSpec, RTLIL::Cell*>::iterator iter = wire_logic_map.find(left[i].wire); std::map<RTLIL::SigSpec, RTLIL::Cell*>::iterator iter = wire_logic_map.find(left[i].wire);
if (iter == wire_logic_map.end()) if (iter == wire_logic_map.end()) {
{
new_left.append(left[i]); new_left.append(left[i]);
} else { } else {
RTLIL::Cell *reduce_cell = iter->second; RTLIL::Cell *reduce_cell = iter->second;
@ -1578,6 +1577,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (child->children.size() > 0) { if (child->children.size() > 0) {
sig = child->children[0]->genRTLIL(); sig = child->children[0]->genRTLIL();
for (int i = 0; i < GetSize(sig); i++) { for (int i = 0; i < GetSize(sig); i++) {
if (sig[i].wire) {
std::map<RTLIL::SigSpec, RTLIL::Cell*>::iterator iter = wire_logic_map.find(sig[i].wire); std::map<RTLIL::SigSpec, RTLIL::Cell*>::iterator iter = wire_logic_map.find(sig[i].wire);
if (iter == wire_logic_map.end()) { if (iter == wire_logic_map.end()) {
new_sig.append(sig[i]); new_sig.append(sig[i]);
@ -1594,6 +1594,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
reduce_cell->fixup_parameters(); reduce_cell->fixup_parameters();
new_sig.append(new_reduce_input); new_sig.append(new_reduce_input);
} }
} else {
new_sig.append(sig[i]);
}
} }
} }
if (child->str.size() == 0) { if (child->str.size() == 0) {