From 85cbd05bb1c6964185435490f1423d76a7140c77 Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Sun, 2 Jun 2024 01:12:43 -0700 Subject: [PATCH] Update some runtime flags to fix some potential issues --- frontends/verific/verific.cc | 5 ++++- verific | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index f97cdab7e..5848f2f06 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3252,6 +3252,9 @@ struct VerificPass : public Pass { RuntimeFlags::SetVar("veri_extract_dualport_rams", 0); RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1); + RuntimeFlags::SetVar("veri_break_loops", 0); // SILIMATE: add to avoid breaking loops + RuntimeFlags::SetVar("veri_optimize_wide_selector", 1); // SILIMATE: add to optimize wide selector + RuntimeFlags::SetVar("veri_ignore_assertion_statements", 1); // SILIMATE: add to ignore SVA/asserts #ifdef VERIFIC_VHDL_SUPPORT RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0); @@ -3276,7 +3279,7 @@ struct VerificPass : public Pass { Message::SetMessageType("VERI-1063", VERIFIC_ERROR); // https://github.com/YosysHQ/yosys/issues/1055 - RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ; + RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 0) ; // SILIMATE: add to resolve bug related to interfaces RuntimeFlags::SetVar("verific_produce_verbose_syntax_error_message", 1); diff --git a/verific b/verific index ce8f924e5..44a6fdd9f 160000 --- a/verific +++ b/verific @@ -1 +1 @@ -Subproject commit ce8f924e56aaf8b3b16156bdc28499c424d6f4b9 +Subproject commit 44a6fdd9f1017959ffd53dafdca75904e5230224