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synth_intel: a10gx -> arria10gx

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This commit is contained in:
Dan Ravensloft 2019-12-10 13:40:32 +00:00
parent eab3272cde
commit 85a14895ca
5 changed files with 4 additions and 4 deletions
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2
techlibs/intel/Makefile.inc
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@ -7,7 +7,7 @@ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k.
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v)) $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v))
# Add the cell models and mappings for the VQM backend # Add the cell models and mappings for the VQM backend
families := max10 a10gx cyclonev cyclone10lp cycloneiv cycloneive families := max10 arria10gx cyclonev cyclone10lp cycloneiv cycloneive
$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v))) $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v)))
$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v))) $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v)))
#$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v)) #$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v))

0
techlibs/intel/a10gx/cells_arith.v → techlibs/intel/arria10gx/cells_arith.v
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0
techlibs/intel/a10gx/cells_map.v → techlibs/intel/arria10gx/cells_map.v
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0
techlibs/intel/a10gx/cells_sim.v → techlibs/intel/arria10gx/cells_sim.v
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6
techlibs/intel/synth_intel.cc
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@ -36,7 +36,7 @@ struct SynthIntelPass : public ScriptPass {
log("\n"); log("\n");
log("This command runs synthesis for Intel FPGAs.\n"); log("This command runs synthesis for Intel FPGAs.\n");
log("\n"); log("\n");
log(" -family <max10 | a10gx | cyclone10lp | cyclonev | cycloneiv | cycloneive>\n"); log(" -family <max10 | arria10gx | cyclone10lp | cyclonev | cycloneiv | cycloneive>\n");
log(" generate the synthesis netlist for the specified family.\n"); log(" generate the synthesis netlist for the specified family.\n");
log(" MAX10 is the default target if no family argument specified.\n"); log(" MAX10 is the default target if no family argument specified.\n");
log(" For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use cycloneive.\n"); log(" For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use cycloneive.\n");
@ -148,7 +148,7 @@ struct SynthIntelPass : public ScriptPass {
if (!design->full_selection()) if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n"); log_cmd_error("This command only operates on fully selected designs!\n");
if (family_opt != "max10" && if (family_opt != "max10" &&
family_opt != "a10gx" && family_opt != "arria10gx" &&
family_opt != "cyclonev" && family_opt != "cyclonev" &&
family_opt != "cycloneiv" && family_opt != "cycloneiv" &&
family_opt != "cycloneive" && family_opt != "cycloneive" &&
@ -214,7 +214,7 @@ struct SynthIntelPass : public ScriptPass {
} }
if (check_label("map_luts")) { if (check_label("map_luts")) {
if (family_opt == "a10gx" || family_opt == "cyclonev") if (family_opt == "arria10gx" || family_opt == "cyclonev")
run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : "")); run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
else else
run("abc -lut 4" + string(retime ? " -dff" : "")); run("abc -lut 4" + string(retime ? " -dff" : ""));