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Various presentation fixes

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This commit is contained in:
Clifford Wolf 2015-02-09 12:02:21 +01:00
parent f889e3d385
commit 85887de547
2 changed files with 15 additions and 8 deletions
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2
manual/PRESENTATION_ExSyn.tex
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@ -268,7 +268,7 @@ memory -nomap; techmap -map my_memory_map.v; memory_map
\end{frame} \end{frame}
\begin{frame}[t, fragile]{\subsecname{} -- Example 1/2} \begin{frame}[t, fragile]{\subsecname{} -- Example 1/2}
\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -6cm]{PRESENTATION_ExSyn/memory_01.pdf}\vss} \vbox to 0cm{\includegraphics[width=0.7\linewidth,trim=0cm 0cm 0cm -10cm]{PRESENTATION_ExSyn/memory_01.pdf}\vss}
\vskip-1cm \vskip-1cm
\begin{columns} \begin{columns}
\column[t]{5cm} \column[t]{5cm}

21
manual/PRESENTATION_Prog.tex
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@ -123,8 +123,9 @@ has been executed.
\subsection{The RTLIL Data Structures} \subsection{The RTLIL Data Structures}
\begin{frame}{\subsecname} \begin{frame}{\subsecname}
The RTLIL data structures are simple structs utilizing C++ {\tt std::} The RTLIL data structures are simple structs utilizing {\tt pool<>} and
containers. {\tt dict<>} containers (drop-in replacementments for {\tt
std::unordered\_set<>} and {\tt std::unordered\_map<>}).
\bigskip \bigskip
\begin{itemize} \begin{itemize}
@ -176,14 +177,14 @@ data structures. Yosys always operates on one active design, but can hold many d
\bigskip \bigskip
\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++] \begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
struct RTLIL::Design { struct RTLIL::Design {
std::map<RTLIL::IdString, RTLIL::Module*> modules_; dict<RTLIL::IdString, RTLIL::Module*> modules_;
... ...
}; };
struct RTLIL::Module { struct RTLIL::Module {
RTLIL::IdString name; RTLIL::IdString name;
std::map<RTLIL::IdString, RTLIL::Wire*> wires_; dict<RTLIL::IdString, RTLIL::Wire*> wires_;
std::map<RTLIL::IdString, RTLIL::Cell*> cells_; dict<RTLIL::IdString, RTLIL::Cell*> cells_;
std::vector<RTLIL::SigSig> connections_; std::vector<RTLIL::SigSig> connections_;
... ...
}; };
@ -293,8 +294,8 @@ instances:
\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++] \begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
struct RTLIL::Cell { struct RTLIL::Cell {
RTLIL::IdString name, type; RTLIL::IdString name, type;
std::map<RTLIL::IdString, RTLIL::SigSpec> connections_; dict<RTLIL::IdString, RTLIL::SigSpec> connections_;
std::map<RTLIL::IdString, RTLIL::Const> parameters; dict<RTLIL::IdString, RTLIL::Const> parameters;
... ...
}; };
\end{lstlisting} \end{lstlisting}
@ -554,6 +555,12 @@ yosys-config --exec --cxx --cxxflags --ldflags \
-o my_cmd.so -shared my_cmd.cc --ldlibs -o my_cmd.so -shared my_cmd.cc --ldlibs
\end{lstlisting} \end{lstlisting}
\bigskip
Or shorter:
\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
yosys-config --build my_cmd.so my_cmd.cc
\end{lstlisting}
\bigskip \bigskip
Load the plugin using the yosys {\tt -m} option: Load the plugin using the yosys {\tt -m} option:
\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont] \begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]