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Merge 3dd3079095 into d0a41d4f58

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Emil J 2025-11-03 10:04:13 +01:00 • committed by GitHub
commit 852b75e483
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22 changed files with 16 additions and 29 deletions
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1
backends/blif/blif.cc
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@ -653,7 +653,6 @@ struct BlifBackend : public Backend {
std::vector<RTLIL::Module*> mod_list;
design->sort();
for (auto module : design->modules())
{
if (module->get_blackbox_attribute() && !config.blackbox_mode)

1
backends/jny/jny.cc
View file

@ -121,7 +121,6 @@ struct JnyWriter
{
log_assert(design != nullptr);
design->sort();
f << "{\n";
f << " \"$schema\": \"https://raw.githubusercontent.com/YosysHQ/yosys/main/misc/jny.schema.json\",\n";

1
backends/json/json.cc
View file

@ -288,7 +288,6 @@ struct JsonWriter
void write_design(Design *design_)
{
design = design_;
design->sort();
f << stringf("{\n");
f << stringf(" \"creator\": %s,\n", get_string(yosys_maybe_version()));

1
backends/table/table.cc
View file

@ -63,7 +63,6 @@ struct TableBackend : public Backend {
}
extra_args(f, filename, args, argidx);
design->sort();
for (auto module : design->modules())
{

2
backends/verilog/verilog_backend.cc
View file

@ -2672,7 +2672,7 @@ struct VerilogBackend : public Backend {
Pass::call(design, "clean_zerowidth");
log_pop();
design->sort_modules();
// design->sort_modules();
*f << stringf("/* Generated by %s */\n", yosys_maybe_version());