mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 17:15:33 +00:00
Code Activity

Fixed cellaigs port extending

Browse source
This commit is contained in:
Clifford Wolf 2015-06-10 07:16:30 +02:00
parent 66f9ee412a
commit 85287295b2
3 changed files with 11 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

2
kernel/cellaigs.cc
View file

@ -77,7 +77,7 @@ struct AigMaker
if (portbit >= GetSize(cell->getPort(portname))) {
if (cell->parameters.count(portname.str() + "_SIGNED") && cell->getParam(portname.str() + "_SIGNED").as_bool())
return inport(portname, GetSize(cell->getPort(portname))-1, inverter);
return bool_node(!inverter);
return bool_node(inverter);
}
AigNode node;