3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-06 11:20:27 +00:00

Added support for initialized xilinx brams

This commit is contained in:
Clifford Wolf 2015-04-06 17:07:10 +02:00
parent 169d1c4711
commit 8520b7fbe0
11 changed files with 313 additions and 90 deletions

View file

@ -3,6 +3,6 @@
set -ex
unisims=/opt/Xilinx/Vivado/2014.4/data/verilog/src/unisims
../../../yosys -v2 -l bram2.log -p synth_xilinx -o bram2_syn.v bram2.v
iverilog -o bram2_tb bram2_tb.v bram2_syn.v -y $unisims $unisims/../glbl.v
iverilog -T typ -o bram2_tb bram2_tb.v bram2_syn.v -y $unisims $unisims/../glbl.v
vvp -N bram2_tb