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Added support for initialized xilinx brams

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This commit is contained in:
Clifford Wolf 2015-04-06 17:07:10 +02:00
parent 169d1c4711
commit 8520b7fbe0
11 changed files with 313 additions and 90 deletions
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17
techlibs/xilinx/tests/bram1.v
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@ -10,10 +10,27 @@ module bram1 #(
input [ABITS-1:0] RD_ADDR,
output [DBITS-1:0] RD_DATA
);
localparam [ABITS-1:0] INIT_ADDR_0 = 1234;
localparam [ABITS-1:0] INIT_ADDR_1 = 4321;
localparam [ABITS-1:0] INIT_ADDR_2 = 2**ABITS-1;
localparam [ABITS-1:0] INIT_ADDR_3 = (2**ABITS-1) / 2;
localparam [DBITS-1:0] INIT_DATA_0 = 128'h 51e152a7300e309ccb8cd06d34558f49;
localparam [DBITS-1:0] INIT_DATA_1 = 128'h 07b1fe94a530ddf3027520f9d23ab43e;
localparam [DBITS-1:0] INIT_DATA_2 = 128'h 3cedc6de43ef3f607af3193658d0eb0b;
localparam [DBITS-1:0] INIT_DATA_3 = 128'h f6bc5514a8abf1e2810df966bcc13b46;
reg [DBITS-1:0] memory [0:2**ABITS-1];
reg [ABITS-1:0] RD_ADDR_BUF;
reg [DBITS-1:0] RD_DATA_BUF;
initial begin
memory[INIT_ADDR_0] <= INIT_DATA_0;
memory[INIT_ADDR_1] <= INIT_DATA_1;
memory[INIT_ADDR_2] <= INIT_DATA_2;
memory[INIT_ADDR_3] <= INIT_DATA_3;
end
always @(posedge clk) begin
if (WR_EN) memory[WR_ADDR] <= WR_DATA;
RD_ADDR_BUF <= RD_ADDR;