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https://github.com/YosysHQ/yosys
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Added support for initialized xilinx brams
This commit is contained in:
Clifford Wolf
parent
169d1c4711
commit
8520b7fbe0
11 changed files with 313 additions and 90 deletions
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@ -1,6 +1,7 @@
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module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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parameter [36863:0] INIT = 36864'bx;
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input CLK2;
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input CLK3;
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@ -32,6 +33,7 @@ module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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.WRITE_MODE_B("READ_FIRST"),
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.IS_CLKARDCLK_INVERTED(!CLKPOL2),
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.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
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`include "brams_init_36.vh"
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.SIM_DEVICE("7SERIES")
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) _TECHMAP_REPLACE_ (
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.DOBDO(DO[63:32]),
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@ -66,6 +68,7 @@ endmodule
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module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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parameter [18431:0] INIT = 18432'bx;
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input CLK2;
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input CLK3;
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@ -94,6 +97,7 @@ module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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.WRITE_MODE_B("READ_FIRST"),
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.IS_CLKARDCLK_INVERTED(!CLKPOL2),
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.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
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`include "brams_init_18.vh"
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.SIM_DEVICE("7SERIES")
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) _TECHMAP_REPLACE_ (
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.DOBDO(DO[31:16]),
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@ -132,6 +136,7 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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parameter [36863:0] INIT = 36864'bx;
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input CLK2;
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input CLK3;
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@ -156,42 +161,83 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
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RAMB36E1 #(
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.RAM_MODE("TDP"),
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.READ_WIDTH_A(CFG_DBITS),
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.READ_WIDTH_B(CFG_DBITS),
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.WRITE_WIDTH_A(CFG_DBITS),
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.WRITE_WIDTH_B(CFG_DBITS),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.IS_CLKARDCLK_INVERTED(!CLKPOL2),
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.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
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.SIM_DEVICE("7SERIES")
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) _TECHMAP_REPLACE_ (
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.DIADI(32'd0),
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.DIPADIP(4'd0),
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.DOADO(DO[31:0]),
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.DOPADOP(DOP[3:0]),
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.ADDRARDADDR(A1ADDR_16),
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.CLKARDCLK(CLK2),
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.ENARDEN(|1),
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.REGCEAREGCE(|1),
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.RSTRAMARSTRAM(|0),
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.RSTREGARSTREG(|0),
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.WEA(4'b0),
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generate if (CFG_DBITS > 8) begin
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RAMB36E1 #(
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.RAM_MODE("TDP"),
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.READ_WIDTH_A(CFG_DBITS),
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.READ_WIDTH_B(CFG_DBITS),
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.WRITE_WIDTH_A(CFG_DBITS),
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.WRITE_WIDTH_B(CFG_DBITS),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.IS_CLKARDCLK_INVERTED(!CLKPOL2),
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.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
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`include "brams_init_36.vh"
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.SIM_DEVICE("7SERIES")
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) _TECHMAP_REPLACE_ (
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.DIADI(32'd0),
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.DIPADIP(4'd0),
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.DOADO(DO[31:0]),
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.DOPADOP(DOP[3:0]),
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.ADDRARDADDR(A1ADDR_16),
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.CLKARDCLK(CLK2),
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.ENARDEN(|1),
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.REGCEAREGCE(|1),
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.RSTRAMARSTRAM(|0),
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.RSTREGARSTREG(|0),
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.WEA(4'b0),
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.DIBDI(DI),
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.DIPBDIP(DIP),
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.DOBDO(DOBDO),
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.DOPBDOP(DOPBDOP),
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.ADDRBWRADDR(B1ADDR_16),
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.CLKBWRCLK(CLK3),
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.ENBWREN(|1),
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.REGCEB(|0),
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.RSTRAMB(|0),
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.RSTREGB(|0),
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.WEBWE(B1EN_8)
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);
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.DIBDI(DI),
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.DIPBDIP(DIP),
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.DOBDO(DOBDO),
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.DOPBDOP(DOPBDOP),
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.ADDRBWRADDR(B1ADDR_16),
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.CLKBWRCLK(CLK3),
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.ENBWREN(|1),
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.REGCEB(|0),
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.RSTRAMB(|0),
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.RSTREGB(|0),
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.WEBWE(B1EN_8)
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);
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end else begin
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RAMB36E1 #(
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.RAM_MODE("TDP"),
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.READ_WIDTH_A(CFG_DBITS),
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.READ_WIDTH_B(CFG_DBITS),
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.WRITE_WIDTH_A(CFG_DBITS),
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.WRITE_WIDTH_B(CFG_DBITS),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.IS_CLKARDCLK_INVERTED(!CLKPOL2),
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.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
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`include "brams_init_32.vh"
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.SIM_DEVICE("7SERIES")
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) _TECHMAP_REPLACE_ (
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.DIADI(32'd0),
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.DIPADIP(4'd0),
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.DOADO(DO[31:0]),
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.DOPADOP(DOP[3:0]),
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.ADDRARDADDR(A1ADDR_16),
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.CLKARDCLK(CLK2),
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.ENARDEN(|1),
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.REGCEAREGCE(|1),
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.RSTRAMARSTRAM(|0),
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.RSTREGARSTREG(|0),
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.WEA(4'b0),
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.DIBDI(DI),
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.DIPBDIP(DIP),
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.DOBDO(DOBDO),
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.DOPBDOP(DOPBDOP),
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.ADDRBWRADDR(B1ADDR_16),
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.CLKBWRCLK(CLK3),
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.ENBWREN(|1),
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.REGCEB(|0),
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.RSTRAMB(|0),
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.RSTREGB(|0),
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.WEBWE(B1EN_8)
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);
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end endgenerate
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endmodule
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// ------------------------------------------------------------------------
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@ -203,6 +249,7 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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parameter [18431:0] INIT = 18432'bx;
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input CLK2;
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input CLK3;
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@ -227,41 +274,82 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
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RAMB18E1 #(
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.RAM_MODE("TDP"),
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.READ_WIDTH_A(CFG_DBITS),
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.READ_WIDTH_B(CFG_DBITS),
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.WRITE_WIDTH_A(CFG_DBITS),
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.WRITE_WIDTH_B(CFG_DBITS),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.IS_CLKARDCLK_INVERTED(!CLKPOL2),
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.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
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.SIM_DEVICE("7SERIES")
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) _TECHMAP_REPLACE_ (
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.DIADI(16'b0),
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.DIPADIP(2'b0),
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.DOADO(DO),
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.DOPADOP(DOP),
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.ADDRARDADDR(A1ADDR_14),
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.CLKARDCLK(CLK2),
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.ENARDEN(|1),
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.REGCEAREGCE(|1),
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.RSTRAMARSTRAM(|0),
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.RSTREGARSTREG(|0),
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.WEA(2'b0),
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generate if (CFG_DBITS > 8) begin
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RAMB18E1 #(
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.RAM_MODE("TDP"),
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.READ_WIDTH_A(CFG_DBITS),
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.READ_WIDTH_B(CFG_DBITS),
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.WRITE_WIDTH_A(CFG_DBITS),
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.WRITE_WIDTH_B(CFG_DBITS),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.IS_CLKARDCLK_INVERTED(!CLKPOL2),
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.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
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`include "brams_init_18.vh"
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.SIM_DEVICE("7SERIES")
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) _TECHMAP_REPLACE_ (
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.DIADI(16'b0),
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.DIPADIP(2'b0),
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.DOADO(DO),
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.DOPADOP(DOP),
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.ADDRARDADDR(A1ADDR_14),
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.CLKARDCLK(CLK2),
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.ENARDEN(|1),
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.REGCEAREGCE(|1),
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.RSTRAMARSTRAM(|0),
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.RSTREGARSTREG(|0),
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.WEA(2'b0),
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.DIBDI(DI),
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.DIPBDIP(DIP),
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.DOBDO(DOBDO),
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.DOPBDOP(DOPBDOP),
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.ADDRBWRADDR(B1ADDR_14),
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.CLKBWRCLK(CLK3),
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.ENBWREN(|1),
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.REGCEB(|0),
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.RSTRAMB(|0),
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.RSTREGB(|0),
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.WEBWE(B1EN_4)
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);
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.DIBDI(DI),
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.DIPBDIP(DIP),
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.DOBDO(DOBDO),
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.DOPBDOP(DOPBDOP),
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.ADDRBWRADDR(B1ADDR_14),
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.CLKBWRCLK(CLK3),
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.ENBWREN(|1),
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.REGCEB(|0),
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.RSTRAMB(|0),
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.RSTREGB(|0),
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.WEBWE(B1EN_4)
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);
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end else begin
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RAMB18E1 #(
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.RAM_MODE("TDP"),
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.READ_WIDTH_A(CFG_DBITS),
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.READ_WIDTH_B(CFG_DBITS),
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.WRITE_WIDTH_A(CFG_DBITS),
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.WRITE_WIDTH_B(CFG_DBITS),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.IS_CLKARDCLK_INVERTED(!CLKPOL2),
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.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
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`include "brams_init_16.vh"
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.SIM_DEVICE("7SERIES")
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) _TECHMAP_REPLACE_ (
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.DIADI(16'b0),
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.DIPADIP(2'b0),
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.DOADO(DO),
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.DOPADOP(DOP),
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.ADDRARDADDR(A1ADDR_14),
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.CLKARDCLK(CLK2),
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.ENARDEN(|1),
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.REGCEAREGCE(|1),
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.RSTRAMARSTRAM(|0),
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.RSTREGARSTREG(|0),
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.WEA(2'b0),
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.DIBDI(DI),
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.DIPBDIP(DIP),
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.DOBDO(DOBDO),
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.DOPBDOP(DOPBDOP),
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.ADDRBWRADDR(B1ADDR_14),
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.CLKBWRCLK(CLK3),
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.ENBWREN(|1),
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.REGCEB(|0),
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.RSTRAMB(|0),
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.RSTREGB(|0),
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.WEBWE(B1EN_4)
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);
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end endgenerate
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endmodule
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