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Fix EDIF: portRef member 0 is always the MSB bit

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This commit is contained in:
Clifford Wolf 2017-03-19 14:53:28 +01:00
parent 1390e9a0a7
commit 850f8299a9
2 changed files with 14 additions and 13 deletions
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9
backends/edif/edif.cc
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@ -317,10 +317,7 @@ struct EdifBackend : public Backend {
*f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(wire->name, port_rename, b[0], b[1]), wire->width, dir);
for (int i = 0; i < wire->width; i++) {
RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i));
if (wire->upto)
net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), GetSize(wire)-i-1));
else
net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i));
net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), GetSize(wire)-i-1));
}
}
}
@ -363,11 +360,11 @@ struct EdifBackend : public Backend {
else if (sig.size() == 1)
net_join_db[sig[i]].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name)));
else {
int member_idx = i;
int member_idx = GetSize(sig)-i-1;
auto m = design->module(cell->type);
if (m) {
auto w = m->wire(p.first);
if (w && w->upto)
if (w)
member_idx = GetSize(w)-i-1;
}
net_join_db[sig[i]].insert(stringf("(portRef (member %s %d) (instanceRef %s))",