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Fix EDIF: portRef member 0 is always the MSB bit

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This commit is contained in:
Clifford Wolf 2017-03-19 14:53:28 +01:00
parent 1390e9a0a7
commit 850f8299a9
2 changed files with 14 additions and 13 deletions
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9
backends/edif/edif.cc
View file

@ -317,10 +317,7 @@ struct EdifBackend : public Backend {
*f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(wire->name, port_rename, b[0], b[1]), wire->width, dir);
for (int i = 0; i < wire->width; i++) {
RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i));
if (wire->upto)
net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), GetSize(wire)-i-1));
else
net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i));
net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), GetSize(wire)-i-1));
}
}
}
@ -363,11 +360,11 @@ struct EdifBackend : public Backend {
else if (sig.size() == 1)
net_join_db[sig[i]].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name)));
else {
int member_idx = i;
int member_idx = GetSize(sig)-i-1;
auto m = design->module(cell->type);
if (m) {
auto w = m->wire(p.first);
if (w && w->upto)
if (w)
member_idx = GetSize(w)-i-1;
}
net_join_db[sig[i]].insert(stringf("(portRef (member %s %d) (instanceRef %s))",

18
backends/edif/runtest.py
View file

@ -5,6 +5,7 @@ import numpy as np
enable_upto = True
enable_offset = True
enable_hierarchy = True
def make_module(f, modname, width, subs):
print("module %s (A, B, C, X, Y, Z);" % modname, file=f)
@ -60,13 +61,16 @@ def make_module(f, modname, width, subs):
print("endmodule", file=f)
with open("test_top.v", "w") as f:
make_module(f, "sub1", 2, {})
make_module(f, "sub2", 3, {})
make_module(f, "sub3", 4, {})
make_module(f, "sub4", 8, {"sub1": 2, "sub2": 3, "sub3": 4})
make_module(f, "sub5", 8, {"sub1": 2, "sub2": 3, "sub3": 4})
make_module(f, "sub6", 8, {"sub1": 2, "sub2": 3, "sub3": 4})
make_module(f, "top", 32, {"sub4": 8, "sub5": 8, "sub6": 8})
if enable_hierarchy:
make_module(f, "sub1", 2, {})
make_module(f, "sub2", 3, {})
make_module(f, "sub3", 4, {})
make_module(f, "sub4", 8, {"sub1": 2, "sub2": 3, "sub3": 4})
make_module(f, "sub5", 8, {"sub1": 2, "sub2": 3, "sub3": 4})
make_module(f, "sub6", 8, {"sub1": 2, "sub2": 3, "sub3": 4})
make_module(f, "top", 32, {"sub4": 8, "sub5": 8, "sub6": 8})
else:
make_module(f, "top", 32, {})
os.system("set -x; ../../yosys -p 'prep -top top; write_edif -pvector par test_syn.edif' test_top.v")