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synth_xilinx: Use opt_dff.
The main part is converting xilinx_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
This commit is contained in:
Marcelina Kościelnicka
parent
4a05cad7f8
commit
8501342fc5
7 changed files with 219 additions and 887 deletions
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@ -51,12 +51,10 @@ state <int> AREG BREG
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// Variables used for subpatterns
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state <SigSpec> argQ argD
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state <bool> ffcepol ffrstpol
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state <int> ffoffset
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udata <SigSpec> dffD dffQ
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udata <SigBit> dffclock
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udata <Cell*> dff dffcemux dffrstmux
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udata <bool> dffcepol dffrstpol
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udata <Cell*> dff
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code
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#define MAX_DSP_CASCADE 20
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@ -254,9 +252,9 @@ code argQ clock AREG
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clock = port(prev, \CLK);
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subpattern(in_dffe);
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if (dff) {
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if (!dffrstmux && port(prev, \RSTA, State::S0) != State::S0)
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if (!dff->type.in($sdff, $sdffe) && port(prev, \RSTA, State::S0) != State::S0)
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goto reject_AREG;
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if (dffrstmux && port(dffrstmux, \S) != port(prev, \RSTA, State::S0))
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if (dff->type.in($sdff, $sdffe) && (port(dff, \SRST) != port(prev, \RSTA, State::S0) || !param(dff, \SRST_POLARITY).as_bool()))
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goto reject_AREG;
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IdString CEA;
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if (param(prev, \AREG) == 1)
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@ -264,9 +262,9 @@ code argQ clock AREG
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else if (param(prev, \AREG) == 2)
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CEA = \CEA1;
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else log_abort();
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if (!dffcemux && port(prev, CEA, State::S0) != State::S1)
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if (!dff->type.in($dffe, $sdffe) && port(prev, CEA, State::S0) != State::S1)
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goto reject_AREG;
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if (dffcemux && port(dffcemux, \S) != port(prev, CEA, State::S0))
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if (dff->type.in($dffe, $sdffe) && (port(dff, \EN) != port(prev, CEA, State::S0) || !param(dff, \EN_POLARITY).as_bool()))
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goto reject_AREG;
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if (dffD == unextend(port(prev, \A)))
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AREG = 1;
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@ -295,9 +293,9 @@ code argQ clock BREG
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clock = port(prev, \CLK);
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subpattern(in_dffe);
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if (dff) {
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if (!dffrstmux && port(prev, \RSTB, State::S0) != State::S0)
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if (!dff->type.in($sdff, $sdffe) && port(prev, \RSTB, State::S0) != State::S0)
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goto reject_BREG;
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if (dffrstmux && port(dffrstmux, \S) != port(prev, \RSTB, State::S0))
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if (dff->type.in($sdff, $sdffe) && (port(dff, \SRST) != port(prev, \RSTB, State::S0) || !param(dff, \SRST_POLARITY).as_bool()))
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goto reject_BREG;
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IdString CEB;
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if (next->type.in(\DSP48A, \DSP48A1))
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@ -310,9 +308,9 @@ code argQ clock BREG
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else log_abort();
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}
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else log_abort();
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if (!dffcemux && port(prev, CEB, State::S0) != State::S1)
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if (!dff->type.in($dffe, $sdffe) && port(prev, CEB, State::S0) != State::S1)
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goto reject_BREG;
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if (dffcemux && port(dffcemux, \S) != port(prev, CEB, State::S0))
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if (dff->type.in($dffe, $sdffe) && (port(dff, \EN) != port(prev, CEB, State::S0) || !param(dff, \EN_POLARITY).as_bool()))
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goto reject_BREG;
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if (dffD == unextend(port(prev, \B))) {
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if (next->type.in(\DSP48A, \DSP48A1) && param(prev, \B0REG) != 0)
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@ -357,25 +355,14 @@ endcode
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// #######################
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// Subpattern for matching against input registers, based on knowledge of the
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// 'Q' input. Typically, identifying registers with clock-enable and reset
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// capability would be a task would be handled by other Yosys passes such as
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// dff2dffe, but since DSP inference happens much before this, these patterns
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// have to be manually identified.
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// At a high level:
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// (1) Starting from a $dff cell that (partially or fully) drives the given
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// 'Q' argument
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// (2) Match for a $mux cell implementing synchronous reset semantics ---
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// one that exclusively drives the 'D' input of the $dff, with one of its
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// $mux inputs being fully zero
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// (3) Match for a $mux cell implement clock enable semantics --- one that
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// exclusively drives the 'D' input of the $dff (or the other input of
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// the reset $mux) and where one of this $mux's inputs is connected to
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// the 'Q' output of the $dff
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// 'Q' input.
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subpattern in_dffe
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arg argD argQ clock
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arg argQ clock
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code
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dff = nullptr;
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if (argQ.empty())
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reject;
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for (const auto &c : argQ.chunks()) {
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// Abandon matches when 'Q' is a constant
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if (!c.wire)
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@ -386,19 +373,21 @@ code
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// Abandon matches when 'Q' has a non-zero init attribute set
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// (not supported by DSP48E1)
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Const init = c.wire->attributes.at(\init, Const());
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for (auto b : init.extract(c.offset, c.width))
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if (b != State::Sx && b != State::S0)
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reject;
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if (!init.empty())
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for (auto b : init.extract(c.offset, c.width))
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if (b != State::Sx && b != State::S0)
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reject;
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}
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endcode
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// (1) Starting from a $dff cell that (partially or fully) drives the given
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// 'Q' argument
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match ff
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select ff->type.in($dff)
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select ff->type.in($dff, $dffe, $sdff, $sdffe)
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// DSP48E1 does not support clock inversion
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select param(ff, \CLK_POLARITY).as_bool()
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// Check that reset value, if present, is fully 0.
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filter ff->type.in($dff, $dffe) || param(ff, \SRST_VALUE).is_fully_zero()
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slice offset GetSize(port(ff, \D))
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index <SigBit> port(ff, \Q)[offset] === argQ[0]
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@ -407,80 +396,14 @@ match ff
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filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
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filter clock == SigBit() || port(ff, \CLK) == clock
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set ffoffset offset
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endmatch
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code argQ argD
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code argQ
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SigSpec Q = port(ff, \Q);
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dff = ff;
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dffclock = port(ff, \CLK);
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dffD = argQ;
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argD = port(ff, \D);
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SigSpec D = port(ff, \D);
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argQ = Q;
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dffD.replace(argQ, argD);
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// Only search for ffrstmux if dffD only
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// has two (ff, ffrstmux) users
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if (nusers(dffD) > 2)
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argD = SigSpec();
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endcode
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// (2) Match for a $mux cell implementing synchronous reset semantics ---
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// exclusively drives the 'D' input of the $dff, with one of the $mux
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// inputs being fully zero
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match ffrstmux
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if !argD.empty()
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select ffrstmux->type.in($mux)
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index <SigSpec> port(ffrstmux, \Y) === argD
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choice <IdString> BA {\B, \A}
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// DSP48E1 only supports reset to zero
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select port(ffrstmux, BA).is_fully_zero()
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define <bool> pol (BA == \B)
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set ffrstpol pol
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semioptional
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endmatch
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code argD
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if (ffrstmux) {
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dffrstmux = ffrstmux;
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dffrstpol = ffrstpol;
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argD = port(ffrstmux, ffrstpol ? \A : \B);
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dffD.replace(port(ffrstmux, \Y), argD);
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// Only search for ffcemux if argQ has at
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// least 3 users (ff, <upstream>, ffrstmux) and
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// dffD only has two (ff, ffrstmux)
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if (!(nusers(argQ) >= 3 && nusers(dffD) == 2))
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argD = SigSpec();
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}
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else
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dffrstmux = nullptr;
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endcode
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// (3) Match for a $mux cell implement clock enable semantics --- one that
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// exclusively drives the 'D' input of the $dff (or the other input of
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// the reset $mux) and where one of this $mux's inputs is connected to
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// the 'Q' output of the $dff
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match ffcemux
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if !argD.empty()
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select ffcemux->type.in($mux)
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index <SigSpec> port(ffcemux, \Y) === argD
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choice <IdString> AB {\A, \B}
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index <SigSpec> port(ffcemux, AB) === argQ
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define <bool> pol (AB == \A)
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set ffcepol pol
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semioptional
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endmatch
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code argD
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if (ffcemux) {
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dffcemux = ffcemux;
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dffcepol = ffcepol;
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argD = port(ffcemux, ffcepol ? \B : \A);
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dffD.replace(port(ffcemux, \Y), argD);
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}
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else
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dffcemux = nullptr;
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dffD.replace(argQ, D);
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endcode
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