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synth_xilinx: Use opt_dff.
The main part is converting xilinx_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
This commit is contained in:
Marcelina Kościelnicka
parent
4a05cad7f8
commit
8501342fc5
7 changed files with 219 additions and 887 deletions
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@ -2,9 +2,7 @@
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// forms the `xilinx_dsp` pass described in xilinx_dsp.cc
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// At a high level, it works as follows:
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// ( 1) Starting from a DSP48E1 cell
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// ( 2) Match the driver of the 'A' input to a possible $dff cell (ADREG)
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// (attached to at most two $mux cells that implement clock-enable or
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// reset functionality, using a subpattern discussed below)
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// ( 2) Match the driver of the 'A' input to a possible $sdffe cell (ADREG)
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// If ADREG matched, treat 'A' input as input of ADREG
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// ( 3) Match the driver of the 'A' and 'D' inputs for a possible $add cell
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// (pre-adder)
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@ -44,7 +42,7 @@
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// DSP48E1 cells inferred from multiply operations by Yosys, as well as for
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// user instantiations that may already contain the cells being packed...
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// (though the latter is currently untested)
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// - Since the $dff-with-optional-clock-enable-or-reset-mux pattern is used
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// - Since the $sdffe pattern is used
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// for each *REG match, it has been factored out into two subpatterns:
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// in_dffe and out_dffe located at the bottom of this file.
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// - Matching for pattern detector features is currently incomplete. For
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@ -57,20 +55,15 @@ pattern xilinx_dsp_pack
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state <SigBit> clock
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state <SigSpec> sigA sigB sigC sigD sigM sigP
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state <IdString> postAddAB postAddMuxAB
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state <bool> ffA1cepol ffA2cepol ffADcepol ffB1cepol ffB2cepol ffDcepol ffMcepol ffPcepol
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state <bool> ffArstpol ffADrstpol ffBrstpol ffDrstpol ffMrstpol ffPrstpol
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state <Cell*> ffAD ffADcemux ffADrstmux ffA1 ffA1cemux ffA1rstmux ffA2 ffA2cemux ffA2rstmux
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state <Cell*> ffB1 ffB1cemux ffB1rstmux ffB2 ffB2cemux ffB2rstmux
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state <Cell*> ffD ffDcemux ffDrstmux ffM ffMcemux ffMrstmux ffP ffPcemux ffPrstmux
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state <Cell*> ffAD ffA1 ffA2
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state <Cell*> ffB1 ffB2
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state <Cell*> ffD ffM ffP
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// Variables used for subpatterns
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state <SigSpec> argQ argD
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state <bool> ffcepol ffrstpol
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state <int> ffoffset
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udata <SigSpec> dffD dffQ
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udata <SigBit> dffclock
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udata <Cell*> dff dffcemux dffrstmux
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udata <bool> dffcepol dffrstpol
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udata <Cell*> dff
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// (1) Starting from a DSP48E1 cell
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match dsp
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@ -115,25 +108,15 @@ code sigA sigB sigC sigD sigM clock
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clock = port(dsp, \CLK, SigBit());
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endcode
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// (2) Match the driver of the 'A' input to a possible $dff cell (ADREG)
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// (attached to at most two $mux cells that implement clock-enable or
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// reset functionality, using a subpattern discussed above)
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// (2) Match the driver of the 'A' input to a possible $sdffe cell (ADREG)
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// If matched, treat 'A' input as input of ADREG
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code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock
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code argQ ffAD sigA clock
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if (param(dsp, \ADREG).as_int() == 0) {
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argQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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ffAD = dff;
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clock = dffclock;
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if (dffrstmux) {
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ffADrstmux = dffrstmux;
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ffADrstpol = dffrstpol;
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}
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if (dffcemux) {
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ffADcemux = dffcemux;
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ffADcepol = dffcepol;
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}
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sigA = dffD;
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}
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}
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@ -172,7 +155,7 @@ endcode
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// (4) If pre-adder was present, find match 'A' input for A2REG
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// If pre-adder was not present, move ADREG to A2REG
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// Then match 'A' input for A1REG
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code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock ffA2 ffA2cemux ffA2rstmux ffA2cepol ffArstpol ffA1 ffA1cemux ffA1rstmux ffA1cepol
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code argQ ffAD sigA clock ffA2 ffA1
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// Only search for ffA2 if there was a pre-adder
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// (otherwise ffA2 would have been matched as ffAD)
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if (preAdd) {
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@ -182,14 +165,6 @@ code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock ffA2 ffA2cem
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if (dff) {
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ffA2 = dff;
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clock = dffclock;
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if (dffrstmux) {
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ffA2rstmux = dffrstmux;
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ffArstpol = dffrstpol;
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}
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if (dffcemux) {
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ffA2cepol = dffcepol;
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ffA2cemux = dffcemux;
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}
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sigA = dffD;
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}
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}
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@ -197,12 +172,8 @@ code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock ffA2 ffA2cem
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// And if there wasn't a pre-adder,
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// move AD register to A
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else if (ffAD) {
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log_assert(!ffA2 && !ffA2cemux && !ffA2rstmux);
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log_assert(!ffA2);
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std::swap(ffA2, ffAD);
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std::swap(ffA2cemux, ffADcemux);
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std::swap(ffA2rstmux, ffADrstmux);
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ffA2cepol = ffADcepol;
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ffArstpol = ffADrstpol;
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}
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// Now attempt to match A1
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@ -210,23 +181,23 @@ code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock ffA2 ffA2cem
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argQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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if ((ffA2rstmux != nullptr) ^ (dffrstmux != nullptr))
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if (dff->type != ffA2->type)
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goto ffA1_end;
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if (dffrstmux) {
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if (ffArstpol != dffrstpol)
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if (dff->type.in($sdff, $sdffe, $sdffce)) {
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if (param(dff, \SRST_POLARITY) != param(ffA2, \SRST_POLARITY))
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goto ffA1_end;
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if (port(ffA2rstmux, \S) != port(dffrstmux, \S))
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if (port(dff, \SRST) != port(ffA2, \SRST))
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goto ffA1_end;
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}
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if (dff->type.in($dffe, $sdffe, $sdffce)) {
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if (param(dff, \EN_POLARITY) != param(ffA2, \EN_POLARITY))
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goto ffA1_end;
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if (port(dff, \EN) != port(ffA2, \EN))
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goto ffA1_end;
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ffA1rstmux = dffrstmux;
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}
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ffA1 = dff;
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clock = dffclock;
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if (dffcemux) {
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ffA1cemux = dffcemux;
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ffA1cepol = dffcepol;
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}
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sigA = dffD;
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ffA1_end: ;
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@ -236,21 +207,13 @@ endcode
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// (5) Match 'B' input for B2REG
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// If B2REG, then match 'B' input for B1REG
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code argQ ffB2 ffB2cemux ffB2rstmux ffB2cepol ffBrstpol sigB clock ffB1 ffB1cemux ffB1rstmux ffB1cepol
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code argQ ffB2 sigB clock ffB1
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if (param(dsp, \BREG).as_int() == 0) {
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argQ = sigB;
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subpattern(in_dffe);
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if (dff) {
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ffB2 = dff;
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clock = dffclock;
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if (dffrstmux) {
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ffB2rstmux = dffrstmux;
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ffBrstpol = dffrstpol;
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}
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if (dffcemux) {
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ffB2cemux = dffcemux;
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ffB2cepol = dffcepol;
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}
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sigB = dffD;
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// Now attempt to match B1
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@ -258,23 +221,23 @@ code argQ ffB2 ffB2cemux ffB2rstmux ffB2cepol ffBrstpol sigB clock ffB1 ffB1cemu
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argQ = sigB;
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subpattern(in_dffe);
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if (dff) {
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if ((ffB2rstmux != nullptr) ^ (dffrstmux != nullptr))
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if (dff->type != ffB2->type)
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goto ffB1_end;
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if (dffrstmux) {
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if (ffBrstpol != dffrstpol)
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if (dff->type.in($sdff, $sdffe, $sdffce)) {
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if (param(dff, \SRST_POLARITY) != param(ffB2, \SRST_POLARITY))
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goto ffB1_end;
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if (port(ffB2rstmux, \S) != port(dffrstmux, \S))
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if (port(dff, \SRST) != port(ffB2, \SRST))
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goto ffB1_end;
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}
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if (dff->type.in($dffe, $sdffe, $sdffce)) {
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if (param(dff, \EN_POLARITY) != param(ffB2, \EN_POLARITY))
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goto ffB1_end;
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if (port(dff, \EN) != port(ffB2, \EN))
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goto ffB1_end;
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ffB1rstmux = dffrstmux;
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}
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ffB1 = dff;
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clock = dffclock;
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if (dffcemux) {
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ffB1cemux = dffcemux;
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ffB1cepol = dffcepol;
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}
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sigB = dffD;
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ffB1_end: ;
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@ -286,42 +249,26 @@ ffB1_end: ;
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endcode
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// (6) Match 'D' input for DREG
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code argQ ffD ffDcemux ffDrstmux ffDcepol ffDrstpol sigD clock
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code argQ ffD sigD clock
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if (param(dsp, \DREG).as_int() == 0) {
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argQ = sigD;
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subpattern(in_dffe);
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if (dff) {
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ffD = dff;
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clock = dffclock;
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if (dffrstmux) {
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ffDrstmux = dffrstmux;
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ffDrstpol = dffrstpol;
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}
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if (dffcemux) {
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ffDcemux = dffcemux;
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ffDcepol = dffcepol;
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}
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sigD = dffD;
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}
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}
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endcode
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// (7) Match 'P' output that exclusively drives an MREG
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code argD ffM ffMcemux ffMrstmux ffMcepol ffMrstpol sigM sigP clock
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code argD ffM sigM sigP clock
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if (param(dsp, \MREG).as_int() == 0 && nusers(sigM) == 2) {
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argD = sigM;
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subpattern(out_dffe);
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if (dff) {
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ffM = dff;
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clock = dffclock;
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if (dffrstmux) {
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ffMrstmux = dffrstmux;
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ffMrstpol = dffrstpol;
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}
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if (dffcemux) {
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ffMcemux = dffcemux;
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ffMcepol = dffcepol;
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}
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sigM = dffQ;
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}
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}
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@ -340,9 +287,7 @@ match postAdd
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select postAdd->type.in($add)
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select GetSize(port(postAdd, \Y)) <= 48
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choice <IdString> AB {\A, \B}
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select nusers(port(postAdd, AB)) <= 3
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filter ffMcemux || nusers(port(postAdd, AB)) == 2
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filter !ffMcemux || nusers(port(postAdd, AB)) == 3
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select nusers(port(postAdd, AB)) == 2
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index <SigBit> port(postAdd, AB)[0] === sigP[0]
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filter GetSize(port(postAdd, AB)) >= GetSize(sigP)
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@ -362,25 +307,14 @@ code sigC sigP
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endcode
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// (9) Match 'P' output that exclusively drives a PREG
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code argD ffP ffPcemux ffPrstmux ffPcepol ffPrstpol sigP clock
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code argD ffP sigP clock
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if (param(dsp, \PREG).as_int() == 0) {
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int users = 2;
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// If ffMcemux and no postAdd new-value net must have three users: ffMcemux, ffM and ffPcemux
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if (ffMcemux && !postAdd) users++;
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if (nusers(sigP) == users) {
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if (nusers(sigP) == 2) {
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argD = sigP;
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subpattern(out_dffe);
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if (dff) {
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ffP = dff;
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clock = dffclock;
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if (dffrstmux) {
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ffPrstmux = dffrstmux;
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ffPrstpol = dffrstpol;
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}
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if (dffcemux) {
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ffPcemux = dffcemux;
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ffPcepol = dffcepol;
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}
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sigP = dffQ;
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}
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}
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@ -441,22 +375,9 @@ endcode
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// #######################
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// Subpattern for matching against input registers, based on knowledge of the
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// 'Q' input. Typically, identifying registers with clock-enable and reset
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// capability would be a task would be handled by other Yosys passes such as
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// dff2dffe, but since DSP inference happens much before this, these patterns
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// have to be manually identified.
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// At a high level:
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// (1) Starting from a $dff cell that (partially or fully) drives the given
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// 'Q' argument
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// (2) Match for a $mux cell implementing synchronous reset semantics ---
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// one that exclusively drives the 'D' input of the $dff, with one of its
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// $mux inputs being fully zero
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// (3) Match for a $mux cell implement clock enable semantics --- one that
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// exclusively drives the 'D' input of the $dff (or the other input of
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// the reset $mux) and where one of this $mux's inputs is connected to
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// the 'Q' output of the $dff
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// 'Q' input.
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subpattern in_dffe
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arg argD argQ clock
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arg argQ clock
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code
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dff = nullptr;
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@ -479,13 +400,14 @@ code
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}
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endcode
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// (1) Starting from a $dff cell that (partially or fully) drives the given
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// 'Q' argument
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match ff
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select ff->type.in($dff)
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select ff->type.in($dff, $dffe, $sdff, $sdffe)
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// DSP48E1 does not support clock inversion
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select param(ff, \CLK_POLARITY).as_bool()
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// Check that reset value, if present, is fully 0.
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filter ff->type.in($dff, $dffe) || param(ff, \SRST_VALUE).is_fully_zero()
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slice offset GetSize(port(ff, \D))
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index <SigBit> port(ff, \Q)[offset] === argQ[0]
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@ -494,82 +416,16 @@ match ff
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filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
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filter clock == SigBit() || port(ff, \CLK) == clock
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set ffoffset offset
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endmatch
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code argQ argD
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code argQ
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SigSpec Q = port(ff, \Q);
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dff = ff;
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dffclock = port(ff, \CLK);
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dffD = argQ;
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argD = port(ff, \D);
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SigSpec D = port(ff, \D);
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argQ = Q;
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dffD.replace(argQ, argD);
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// Only search for ffrstmux if dffD only
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// has two (ff, ffrstmux) users
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if (nusers(dffD) > 2)
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argD = SigSpec();
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endcode
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// (2) Match for a $mux cell implementing synchronous reset semantics ---
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// exclusively drives the 'D' input of the $dff, with one of the $mux
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// inputs being fully zero
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match ffrstmux
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if !argD.empty()
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select ffrstmux->type.in($mux)
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index <SigSpec> port(ffrstmux, \Y) === argD
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choice <IdString> BA {\B, \A}
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// DSP48E1 only supports reset to zero
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select port(ffrstmux, BA).is_fully_zero()
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define <bool> pol (BA == \B)
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set ffrstpol pol
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semioptional
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endmatch
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code argD
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if (ffrstmux) {
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dffrstmux = ffrstmux;
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dffrstpol = ffrstpol;
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argD = port(ffrstmux, ffrstpol ? \A : \B);
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dffD.replace(port(ffrstmux, \Y), argD);
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// Only search for ffcemux if argQ has at
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// least 3 users (ff, <upstream>, ffrstmux) and
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// dffD only has two (ff, ffrstmux)
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if (!(nusers(argQ) >= 3 && nusers(dffD) == 2))
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argD = SigSpec();
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}
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else
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dffrstmux = nullptr;
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endcode
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// (3) Match for a $mux cell implement clock enable semantics --- one that
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// exclusively drives the 'D' input of the $dff (or the other input of
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// the reset $mux) and where one of this $mux's inputs is connected to
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// the 'Q' output of the $dff
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match ffcemux
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if !argD.empty()
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select ffcemux->type.in($mux)
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index <SigSpec> port(ffcemux, \Y) === argD
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choice <IdString> AB {\A, \B}
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index <SigSpec> port(ffcemux, AB) === argQ
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define <bool> pol (AB == \A)
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set ffcepol pol
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semioptional
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endmatch
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code argD
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if (ffcemux) {
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dffcemux = ffcemux;
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dffcepol = ffcepol;
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argD = port(ffcemux, ffcepol ? \B : \A);
|
||||
dffD.replace(port(ffcemux, \Y), argD);
|
||||
}
|
||||
else
|
||||
dffcemux = nullptr;
|
||||
dffD.replace(argQ, D);
|
||||
endcode
|
||||
|
||||
// #######################
|
||||
|
|
@ -597,119 +453,26 @@ code
|
|||
reject;
|
||||
endcode
|
||||
|
||||
// (1) Starting from an optional $mux cell that implements clock enable
|
||||
// semantics --- one where the given 'D' argument (partially or fully)
|
||||
// drives one of its two inputs
|
||||
match ffcemux
|
||||
select ffcemux->type.in($mux)
|
||||
// ffcemux output must have two users: ffcemux and ff.D
|
||||
select nusers(port(ffcemux, \Y)) == 2
|
||||
|
||||
choice <IdString> AB {\A, \B}
|
||||
// keep-last-value net must have at least three users: ffcemux, ff, downstream sink(s)
|
||||
select nusers(port(ffcemux, AB)) >= 3
|
||||
|
||||
slice offset GetSize(port(ffcemux, \Y))
|
||||
define <IdString> BA (AB == \A ? \B : \A)
|
||||
index <SigBit> port(ffcemux, BA)[offset] === argD[0]
|
||||
|
||||
// Check that the rest of argD is present
|
||||
filter GetSize(port(ffcemux, BA)) >= offset + GetSize(argD)
|
||||
filter port(ffcemux, BA).extract(offset, GetSize(argD)) == argD
|
||||
|
||||
set ffoffset offset
|
||||
define <bool> pol (AB == \A)
|
||||
set ffcepol pol
|
||||
|
||||
semioptional
|
||||
endmatch
|
||||
|
||||
code argD argQ
|
||||
dffcemux = ffcemux;
|
||||
if (ffcemux) {
|
||||
SigSpec BA = port(ffcemux, ffcepol ? \B : \A);
|
||||
SigSpec Y = port(ffcemux, \Y);
|
||||
argQ = argD;
|
||||
argD.replace(BA, Y);
|
||||
argQ.replace(BA, port(ffcemux, ffcepol ? \A : \B));
|
||||
|
||||
dffcemux = ffcemux;
|
||||
dffcepol = ffcepol;
|
||||
}
|
||||
endcode
|
||||
|
||||
// (2) Starting from, or continuing onto, another optional $mux cell that
|
||||
// implements synchronous reset semantics --- one where the given 'D'
|
||||
// argument (or the clock enable $mux output) drives one of its two inputs
|
||||
// and where the other input is fully zero
|
||||
match ffrstmux
|
||||
select ffrstmux->type.in($mux)
|
||||
// ffrstmux output must have two users: ffrstmux and ff.D
|
||||
select nusers(port(ffrstmux, \Y)) == 2
|
||||
|
||||
choice <IdString> BA {\B, \A}
|
||||
// DSP48E1 only supports reset to zero
|
||||
select port(ffrstmux, BA).is_fully_zero()
|
||||
|
||||
slice offset GetSize(port(ffrstmux, \Y))
|
||||
define <IdString> AB (BA == \B ? \A : \B)
|
||||
index <SigBit> port(ffrstmux, AB)[offset] === argD[0]
|
||||
|
||||
// Check that offset is consistent
|
||||
filter !ffcemux || ffoffset == offset
|
||||
// Check that the rest of argD is present
|
||||
filter GetSize(port(ffrstmux, AB)) >= offset + GetSize(argD)
|
||||
filter port(ffrstmux, AB).extract(offset, GetSize(argD)) == argD
|
||||
|
||||
set ffoffset offset
|
||||
define <bool> pol (AB == \A)
|
||||
set ffrstpol pol
|
||||
|
||||
semioptional
|
||||
endmatch
|
||||
|
||||
code argD argQ
|
||||
dffrstmux = ffrstmux;
|
||||
if (ffrstmux) {
|
||||
SigSpec AB = port(ffrstmux, ffrstpol ? \A : \B);
|
||||
SigSpec Y = port(ffrstmux, \Y);
|
||||
argD.replace(AB, Y);
|
||||
|
||||
dffrstmux = ffrstmux;
|
||||
dffrstpol = ffrstpol;
|
||||
}
|
||||
endcode
|
||||
|
||||
// (3) Match for a $dff cell (whose 'D' input is the 'D' argument, or the
|
||||
// output of the previous clock enable or reset $mux cells)
|
||||
match ff
|
||||
select ff->type.in($dff)
|
||||
select ff->type.in($dff, $dffe, $sdff, $sdffe)
|
||||
// DSP48E1 does not support clock inversion
|
||||
select param(ff, \CLK_POLARITY).as_bool()
|
||||
|
||||
slice offset GetSize(port(ff, \D))
|
||||
index <SigBit> port(ff, \D)[offset] === argD[0]
|
||||
|
||||
// Check that offset is consistent
|
||||
filter (!ffcemux && !ffrstmux) || ffoffset == offset
|
||||
// Check that the rest of argD is present
|
||||
filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
|
||||
filter port(ff, \D).extract(offset, GetSize(argD)) == argD
|
||||
// Check that FF.Q is connected to CE-mux
|
||||
filter !ffcemux || port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
|
||||
|
||||
filter clock == SigBit() || port(ff, \CLK) == clock
|
||||
|
||||
set ffoffset offset
|
||||
endmatch
|
||||
|
||||
code argQ
|
||||
SigSpec D = port(ff, \D);
|
||||
SigSpec Q = port(ff, \Q);
|
||||
if (!ffcemux) {
|
||||
argQ = argD;
|
||||
argQ.replace(D, Q);
|
||||
}
|
||||
argQ = argD;
|
||||
argQ.replace(D, Q);
|
||||
|
||||
// Abandon matches when 'Q' has a non-zero init attribute set
|
||||
// (not supported by DSP48E1)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue