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Add more SVA test cases for future Verific work

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This commit is contained in:
Clifford Wolf 2017-07-22 16:35:46 +02:00
parent 5be535517c
commit 84f15260b5
5 changed files with 74 additions and 1 deletions
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2
tests/sva/basic02.sv
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@ -13,4 +13,4 @@ module top_properties (input logic clock, read, write, ready);
a_wr: assert property ( @(posedge clock) write |-> ready );
endmodule
bind top top_properties inst (.*);
bind top top_properties properties_inst (.*);

6
tests/sva/basic04.sv Normal file
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@ -0,0 +1,6 @@
module top_properties (input logic clock, read, write, ready);
a_rw: assert property ( @(posedge clock) !(read && write) );
a_wr: assert property ( @(posedge clock) write |-> ready );
endmodule
bind top top_properties properties_inst (.*);

26
tests/sva/basic04.vhd Normal file
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@ -0,0 +1,26 @@
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
clock : in std_logic;
ctrl : in std_logic;
x : out std_logic
);
end entity;
architecture rtl of top is
signal read : std_logic;
signal write : std_logic;
signal ready : std_logic;
begin
process (clock) begin
if (rising_edge(clock)) then
read <= not ctrl;
write <= ctrl;
ready <= write;
end if;
end process;
x <= read xor write xor ready;
end architecture;

15
tests/sva/basic05.sv Normal file
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@ -0,0 +1,15 @@
module top (input logic clock, ctrl);
logic read, write, ready;
demo uut (
.clock(clock),
.ctrl(ctrl)
);
assign read = uut.read;
assign write = uut.write;
assign ready = uut.ready;
a_rw: assert property ( @(posedge clock) !(read && write) );
a_wr: assert property ( @(posedge clock) write |-> ready );
endmodule

26
tests/sva/basic05.vhd Normal file
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@ -0,0 +1,26 @@
library ieee;
use ieee.std_logic_1164.all;
entity demo is
port (
clock : in std_logic;
ctrl : in std_logic;
x : out std_logic
);
end entity;
architecture rtl of demo is
signal read : std_logic;
signal write : std_logic;
signal ready : std_logic;
begin
process (clock) begin
if (rising_edge(clock)) then
read <= not ctrl;
write <= ctrl;
ready <= write;
end if;
end process;
x <= read xor write xor ready;
end architecture;