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Add more SVA test cases for future Verific work

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This commit is contained in:
Clifford Wolf 2017-07-22 16:35:46 +02:00
parent 5be535517c
commit 84f15260b5
5 changed files with 74 additions and 1 deletions
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tests/sva/basic04.sv Normal file
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module top_properties (input logic clock, read, write, ready);
a_rw: assert property ( @(posedge clock) !(read && write) );
a_wr: assert property ( @(posedge clock) write |-> ready );
endmodule
bind top top_properties properties_inst (.*);