mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-10 05:00:52 +00:00
Code Activity

Spell check (by Larry Doolittle)

Browse source
This commit is contained in:
Clifford Wolf 2015-08-14 10:56:05 +02:00
parent 80910d13a6
commit 84bf862f7c
63 changed files with 220 additions and 220 deletions
Download patch file Download diff file Expand all files Collapse all files

36
manual/PRESENTATION_Intro.tex
View file

@ -31,12 +31,12 @@
\only<3>{Netlists}%
\only<4>{Hardware Description Languages (HDLs)}}
\only<1>{
Graphical representation of the circtuit topology. Circuit elements
are represented by symbols and electrical connections by lines. The gometric
Graphical representation of the circuit topology. Circuit elements
are represented by symbols and electrical connections by lines. The geometric
layout is for readability only.
}%
\only<2>{
The actual physical geometry of the device (PCB or ASIC manufracturing masks).
The actual physical geometry of the device (PCB or ASIC manufacturing masks).
This is the final product of the design process.
}%
\only<3>{
@ -86,7 +86,7 @@
}%
\only<4>{
List of registers (flip-flops) and logic functions that calculate the next state from the previous one. Usually
a netlist utilizing high-level cells such as adders, multiplieres, multiplexer, etc.
a netlist utilizing high-level cells such as adders, multipliers, multiplexer, etc.
}%
\only<5>{
Netlist of single-bit registers and basic logic gates (such as AND, OR,
@ -95,7 +95,7 @@
}%
\only<6>{
Netlist of cells that actually are available on the target architecture
(such as CMOS gates in an ASCI or LUTs in an FPGA). Optimized for
(such as CMOS gates in an ASIC or LUTs in an FPGA). Optimized for
area, power, and/or speed (static timing or number of logic levels).
}%
\only<7>{
@ -155,7 +155,7 @@ Things Yosys can do:
\begin{itemize}
\item Read and process (most of) modern Verilog-2005 code.
\item Perform all kinds of operations on netlist (RTL, Logic, Gate).
\item Perform logic optimiziations and gate mapping with ABC\footnote[frame]{\url{http://www.eecs.berkeley.edu/~alanmi/abc/}}.
\item Perform logic optimizations and gate mapping with ABC\footnote[frame]{\url{http://www.eecs.berkeley.edu/~alanmi/abc/}}.
\end{itemize}
\bigskip
@ -176,7 +176,7 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
\subsection{Yosys Data- and Control-Flow}
\begin{frame}{\subsecname}
A (usually short) synthesis script controlls Yosys.
A (usually short) synthesis script controls Yosys.
This scripts contain three types of commands:
\begin{itemize}
@ -658,7 +658,7 @@ endmodule
\subsection{Verification of Yosys}
\begin{frame}{\subsecname}
Contiously checking the correctness of Yosys and making sure that new features
Continuously checking the correctness of Yosys and making sure that new features
do not break old ones is a high priority in Yosys.
\bigskip
@ -697,7 +697,7 @@ the other tools used as external reference where found and reported so far.
\begin{frame}{\subsecname{} -- yosys-bigsim}
yosys-bigsim is a collection of real-world open-source Verilog designs and test
benches. yosys-bigsim compares the testbench outpus of simulations of the original
benches. yosys-bigsim compares the testbench outputs of simulations of the original
Verilog code and synthesis results.
\bigskip
@ -721,7 +721,7 @@ The following designs are included in yosys-bigsim (excerpt):
\begin{frame}{\subsecname}
\begin{itemize}
\item Cost (also applies to ``free as in free beer'' solutions)
\item Availablity and Reproducability
\item Availability and Reproducibility
\item Framework- and all-in-one-aspects
\item Educational Tool
\end{itemize}
@ -739,7 +739,7 @@ the cost for the design tools needed to design the mask layouts. Open Source
ASIC flows are an important enabler for ASIC-level Open Source Hardware.
\bigskip
\item Availablity and Reproducability: \smallskip\par
\item Availability and Reproducibility: \smallskip\par
If you are a researcher who is publishing, you want to use tools that everyone
else can also use. Even if most universities have access to all major
commercial tools, you usually do not have easy access to the version that was
@ -757,9 +757,9 @@ basic functionality. Extensibility was one of Yosys' design goals.
\bigskip
\item All-in-one: \smallskip\par
Because of the framework characterisitcs of Yosys, an increasing number of features
Because of the framework characteristics of Yosys, an increasing number of features
become available in one tool. Yosys not only can be used for circuit synthesis but
also for formal equivialence checking, SAT solving, and for circuit analysis, to
also for formal equivalence checking, SAT solving, and for circuit analysis, to
name just a few other application domains. With proprietary software one needs to
learn a new tool for each of this applications.
\end{itemize}
@ -768,7 +768,7 @@ learn a new tool for each of this applications.
\begin{frame}{\subsecname{} -- 3/3}
\begin{itemize}
\item Educational Tool: \smallskip\par
Propritaery synthesis tools are at times very secretive about their inner
Proprietary synthesis tools are at times very secretive about their inner
workings. They often are ``black boxes''. Yosys is very open about its
internals and it is easy to observe the different steps of synthesis.
\end{itemize}
@ -789,8 +789,8 @@ copyright notice and this permission notice appear in all copies.
\begin{itemize}
\item Synthesis of final production designs
\item Pre-production synthesis (trial runs before investing in other tools)
\item Convertion of full-featured Verilog to simple Verilog
\item Convertion of Verilog to other formats (BLIF, BTOR, etc)
\item Conversion of full-featured Verilog to simple Verilog
\item Conversion of Verilog to other formats (BLIF, BTOR, etc)
\item Demonstrating synthesis algorithms (e.g. for educational purposes)
\item Framework for experimenting with new algorithms
\item Framework for building custom flows\footnote[frame]{Not limited to synthesis
@ -908,7 +908,7 @@ control logic because it is simpler than setting up a commercial flow.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Documentation, Downloads, Contatcs}
\subsection{Documentation, Downloads, Contacts}
\begin{frame}{\subsecname}
\begin{itemize}
@ -916,7 +916,7 @@ control logic because it is simpler than setting up a commercial flow.
\smallskip\hskip1cm\url{http://www.clifford.at/yosys/}
\bigskip
\item Manual, Command Reference, Appliction Notes: \\
\item Manual, Command Reference, Application Notes: \\
\smallskip\hskip1cm\url{http://www.clifford.at/yosys/documentation.html}
\bigskip