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Clifford Wolf 2015-08-14 10:56:05 +02:00
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manual/CHAPTER_StateOfTheArt.tex
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@ -248,7 +248,7 @@ passes). This architecture will simplify implementing additional HDL front
ends and/or additional synthesis passes.
Chapter~\ref{chapter:eval} contains a more detailed evaluation of Yosys using real-world
designes that are far out of reach for any of the other tools discussed in this appendix.
designs that are far out of reach for any of the other tools discussed in this appendix.
\vskip2cm
\begin{table}[h]