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Clifford Wolf 2015-08-14 10:56:05 +02:00
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manual/CHAPTER_StateOfTheArt/simlib_yosys.v
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@ -19,7 +19,7 @@
*
* The internal logic cell simulation library.
*
* This verilog library contains simple simulation models for the internal
* This Verilog library contains simple simulation models for the internal
* logic cells (_NOT_, _AND_, ...) that are generated by the default technology
* mapper (see "stdcells.v" in this directory) and expected by the "abc" pass.
*