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Added counters sat test case

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Clifford Wolf 2014-02-06 01:00:11 +01:00
parent e915043144
commit 849fd62cfe
2 changed files with 45 additions and 0 deletions
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tests/sat/counters.ys Normal file
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read_verilog counters.v
proc; opt
expose -shared counter1 counter2
miter -equiv -make_assert -make_outputs counter1 counter2 miter
cd miter; flatten; opt
sat -verify -prove-asserts -tempinduct -set-at 1 in_rst 1 -seq 1 -show-inputs -show-outputs