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machxo2: Add dff.ys test, fix another cells_map.v typo.

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William D. Jones 2020-11-17 14:35:17 -05:00 • committed by Marcelina Kościelnicka
parent 044393b990
commit 84937e9689
2 changed files with 11 additions and 1 deletions
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tests/arch/machxo2/dffs.ys Normal file
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read_verilog ../common/dffs.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:FACADE_FF
select -assert-none t:FACADE_FF %% t:* %D