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Merge pull request #1359 from YosysHQ/xc7dsp

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DSP inference for Xilinx (improved for ice40, initial support for ecp5)
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Eddie Hung 2019-09-29 11:26:22 -07:00 • committed by GitHub
commit 8474c5b366
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44 changed files with 6247 additions and 294 deletions
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38
tests/ice40/macc.v
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@ -13,13 +13,35 @@ reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c;
assign c = reg_tmp_c;
always @(posedge clk)
begin
if(set)
begin
reg_tmp_c <= 0;
end
else
begin
reg_tmp_c <= a * b + c;
end
if(set)
begin
reg_tmp_c <= 0;
end
else
begin
reg_tmp_c <= a * b + c;
end
end
endmodule
module top2(clk,a,b,c,hold);
parameter A_WIDTH = 6 /*4*/;
parameter B_WIDTH = 6 /*3*/;
input hold;
input clk;
input signed [(A_WIDTH - 1):0] a;
input signed [(B_WIDTH - 1):0] b;
output signed [(A_WIDTH + B_WIDTH - 1):0] c;
reg signed [A_WIDTH-1:0] reg_a;
reg signed [B_WIDTH-1:0] reg_b;
reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c;
assign c = reg_tmp_c;
always @(posedge clk)
begin
if (!hold) begin
reg_a <= a;
reg_b <= b;
reg_tmp_c <= reg_a * reg_b + c;
end
end
endmodule

24
tests/ice40/macc.ys
View file

@ -1,13 +1,25 @@
read_verilog macc.v
proc
design -save read
hierarchy -top top
#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 -dsp
async2sync
equiv_opt -run prove: -assert null
equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_MAC16
select -assert-none t:SB_MAC16 %% t:* %D
design -load read
hierarchy -top top2
#equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
equiv_opt -run :prove -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
clk2fflogic
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -set-init-zero -seq 4 -verify -prove-asserts -show-ports miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top2 # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_MAC16
select -assert-none t:SB_MAC16 %% t:* %D