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cxxrtl: WIP: adjust comb display cells to only fire on change
Naming and use of statics to be possibly revised.
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parent
7f7c61c9f0
commit
843ad9331b
8 changed files with 95 additions and 16 deletions
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@ -850,7 +850,7 @@ std::ostream &operator<<(std::ostream &os, const value_formatted<Bits> &vf)
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while (!val.is_zero()) {
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value<Bits> quotient;
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val.divideWithRemainder(value<Bits>{10u}, quotient);
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buf += '0' + val.template slice<3, 0>().val().template get<uint8_t>();
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buf += '0' + val.template trunc<(Bits > 4 ? 4 : Bits)>().val().template get<uint8_t>();
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val = quotient;
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}
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if (negative || vf.plus)
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@ -1217,8 +1217,18 @@ struct CxxrtlWorker {
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// $print cell
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} else if (cell->type == ID($print)) {
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log_assert(!for_debug);
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auto trg_enable = cell->getParam(ID::TRG_ENABLE).as_bool();
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static int cell_counter = 0;
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if (!trg_enable) {
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++cell_counter;
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f << indent << "static bool last_print_" << cell_counter << "_known = false;\n";
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f << indent << "static value<1> last_print_" << cell_counter << "_en;\n";
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f << indent << "static value<" << cell->getPort(ID::ARGS).size() << "> last_print_" << cell_counter << "_args;\n";
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}
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f << indent << "if (";
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if (cell->getParam(ID::TRG_ENABLE).as_bool()) {
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if (trg_enable) {
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f << '(';
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for (size_t i = 0; i < (size_t)cell->getParam(ID::TRG_WIDTH).as_int(); i++) {
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RTLIL::SigBit trg_bit = cell->getPort(ID::TRG)[i];
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@ -1235,6 +1245,17 @@ struct CxxrtlWorker {
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f << mangle(trg_bit);
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}
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f << ") && ";
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} else {
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f << '(';
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f << "!last_print_" << cell_counter << "_known || ";
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f << '(';
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f << "last_print_" << cell_counter << "_en != ";
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dump_sigspec_rhs(cell->getPort(ID::EN));
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f << " || last_print_" << cell_counter << "_args != ";
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dump_sigspec_rhs(cell->getPort(ID::ARGS));
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f << ')';
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f << ") && ";
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}
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dump_sigspec_rhs(cell->getPort(ID::EN));
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f << " == value<1>{1u}) {\n";
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@ -1242,6 +1263,16 @@ struct CxxrtlWorker {
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dump_print(cell);
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dec_indent();
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f << indent << "}\n";
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if (!trg_enable) {
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f << indent << "last_print_" << cell_counter << "_known = true;\n";
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f << indent << "last_print_" << cell_counter << "_en = ";
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dump_sigspec_rhs(cell->getPort(ID::EN));
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f << ";\n";
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f << indent << "last_print_" << cell_counter << "_args = ";
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dump_sigspec_rhs(cell->getPort(ID::ARGS));
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f << ";\n";
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}
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// Flip-flops
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} else if (is_ff_cell(cell->type)) {
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log_assert(!for_debug);
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