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opt_expr: Optimize multiplications with low 0 bits in operands.

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Fixes #1500.
This commit is contained in:
Marcelina Kościelnicka 2020-04-12 22:37:44 +02:00
parent 5448f9c85d
commit 840bb17089
2 changed files with 61 additions and 0 deletions
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28
tests/opt/opt_expr.ys
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@ -291,3 +291,31 @@ check
equiv_opt -assert opt_expr -keepdc
design -load postopt
select -assert-count 1 t:$shift r:A_WIDTH=13 %i
###########
design -reset
read_verilog -icells <<EOT
module opt_expr_mul_low_bits(input [2:0] a, input [2:0] b, output [7:0] y);
\$mul #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(8)) mul (.A({a, 1'b0}), .B({b, 1'b0}), .Y(y));
endmodule
EOT
check
equiv_opt -assert opt_expr
design -load postopt
select -assert-count 1 t:$mul r:A_WIDTH=3 %i r:B_WIDTH=3 %i r:Y_WIDTH=6 %i
###########
design -reset
read_verilog -icells <<EOT
module opt_expr_mul_low_bits(input [2:0] a, input [2:0] b, output [7:0] y);
\$mul #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(8)) mul (.A({a, 1'b0}), .B({b, 1'b0}), .Y(y));
endmodule
EOT
check
equiv_opt -assert opt_expr -keepdc
design -load postopt
select -assert-count 1 t:$mul r:A_WIDTH=4 %i r:B_WIDTH=4 %i r:Y_WIDTH=8 %i