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Add some tests

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Copied from Efinix.

* fsm is broken
* latch and tribuf are not implemented yet
* memory maps to dram
This commit is contained in:
Pepijn de Vos 2019-10-21 16:25:15 +02:00
parent 03457ee13e
commit 83fbfe0964
10 changed files with 224 additions and 0 deletions
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3
tests/arch/gowin/.gitignore vendored Normal file
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/*.log
/*.out
/run-test.mk

13
tests/arch/gowin/add_sub.ys Normal file
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read_verilog ../common/add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 8 t:ALU
select -assert-count 8 t:OBUF
select -assert-count 8 t:IBUF
select -assert-count 1 t:GND
select -assert-count 1 t:VCC
select -assert-none t:ALU t:OBUF t:IBUF t:GND t:VCC %% t:* %D

55
tests/arch/gowin/adffs.ys Normal file
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read_verilog ../common/adffs.v
design -save read
hierarchy -top adff
proc
equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:DFFC
select -assert-count 3 t:IBUF
select -assert-count 1 t:OBUF
select -assert-none t:DFFC t:IBUF t:OBUF %% t:* %D
design -load read
hierarchy -top adffn
proc
equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module
select -assert-count 1 t:DFFC
select -assert-count 1 t:LUT1
select -assert-count 3 t:IBUF
select -assert-count 1 t:OBUF
select -assert-none t:DFFC t:IBUF t:OBUF t:LUT1 %% t:* %D
design -load read
hierarchy -top dffs
proc
equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
select -assert-count 1 t:DFFS
select -assert-count 4 t:IBUF
select -assert-count 1 t:OBUF
select -assert-none t:DFFS t:IBUF t:OBUF %% t:* %D
design -load read
hierarchy -top ndffnr
proc
equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module
select -assert-count 1 t:DFFNR
select -assert-count 1 t:LUT1
select -assert-count 4 t:IBUF
select -assert-count 1 t:OBUF
select -assert-none t:DFFNR t:IBUF t:OBUF t:LUT1 %% t:* %D

15
tests/arch/gowin/counter.ys Normal file
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read_verilog ../common/counter.v
hierarchy -top top
proc
flatten
equiv_opt -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 8 t:DFFC
select -assert-count 8 t:ALU
select -assert-count 1 t:GND
select -assert-count 1 t:VCC
select -assert-count 2 t:IBUF
select -assert-count 8 t:OBUF
select -assert-none t:DFFC t:ALU t:GND t:VCC t:IBUF t:OBUF %% t:* %D

25
tests/arch/gowin/dffs.ys Normal file
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read_verilog ../common/dffs.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:DFF
select -assert-count 2 t:IBUF
select -assert-count 1 t:OBUF
select -assert-none t:DFF t:IBUF t:OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:DFFE
select -assert-count 3 t:IBUF
select -assert-count 1 t:OBUF
select -assert-none t:DFFE t:IBUF t:OBUF %% t:* %D

13
tests/arch/gowin/logic.ys Normal file
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read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT1
select -assert-count 6 t:LUT2
select -assert-count 2 t:LUT4
select -assert-count 8 t:IBUF
select -assert-count 10 t:OBUF
select -assert-none t:LUT1 t:LUT2 t:LUT4 t:IBUF t:OBUF %% t:* %D

18
tests/arch/gowin/memory.ys Normal file
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read_verilog ../common/memory.v
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#ERROR: Called with -verify and proof did fail!
#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 8 t:RAM16S4
# other logic present that is not simple
#select -assert-none t:RAM16S4 %% t:* %D

50
tests/arch/gowin/mux.ys Normal file
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read_verilog ../common/mux.v
design -save read
hierarchy -top mux2
proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux2 # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT3
select -assert-count 3 t:IBUF
select -assert-count 1 t:OBUF
select -assert-none t:LUT3 t:IBUF t:OBUF %% t:* %D
design -load read
hierarchy -top mux4
proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 2 t:LUT4
select -assert-count 6 t:IBUF
select -assert-count 1 t:OBUF
select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D
design -load read
hierarchy -top mux8
proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 5 t:LUT4
select -assert-count 11 t:IBUF
select -assert-count 1 t:OBUF
select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D
design -load read
hierarchy -top mux16
proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-count 9 t:LUT4
select -assert-count 3 t:LUT3
select -assert-count 20 t:IBUF
select -assert-count 1 t:OBUF
select -assert-none t:LUT4 t:LUT3 t:IBUF t:OBUF %% t:* %D

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tests/arch/gowin/run-test.sh Executable file
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#!/usr/bin/env bash
set -e
{
echo "all::"
for x in *.ys; do
echo "all:: run-$x"
echo "run-$x:"
echo " @echo 'Running $x..'"
echo " @../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
done
for s in *.sh; do
if [ "$s" != "run-test.sh" ]; then
echo "all:: run-$s"
echo "run-$s:"
echo " @echo 'Running $s..'"
echo " @bash $s"
fi
done
} > run-test.mk
exec ${MAKE:-make} -f run-test.mk

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tests/arch/gowin/shifter.ys Normal file
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read_verilog ../common/shifter.v
hierarchy -top top
proc
flatten
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 8 t:DFF
select -assert-count 2 t:IBUF
select -assert-count 8 t:OBUF
select -assert-none t:DFF t:IBUF t:OBUF %% t:* %D