mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-01 20:17:55 +00:00
Code Activity

Add some tests

Browse source 
Copied from Efinix.

* fsm is broken
* latch and tribuf are not implemented yet
* memory maps to dram
This commit is contained in:
Pepijn de Vos 2019-10-21 16:25:15 +02:00
parent 03457ee13e
commit 83fbfe0964
10 changed files with 224 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

18
tests/arch/gowin/memory.ys Normal file
View file

@ -0,0 +1,18 @@
read_verilog ../common/memory.v
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#ERROR: Called with -verify and proof did fail!
#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 8 t:RAM16S4
# other logic present that is not simple
#select -assert-none t:RAM16S4 %% t:* %D