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Add some tests

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Copied from Efinix.

* fsm is broken
* latch and tribuf are not implemented yet
* memory maps to dram
This commit is contained in:
Pepijn de Vos 2019-10-21 16:25:15 +02:00
parent 03457ee13e
commit 83fbfe0964
10 changed files with 224 additions and 0 deletions
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13
tests/arch/gowin/logic.ys Normal file
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read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT1
select -assert-count 6 t:LUT2
select -assert-count 2 t:LUT4
select -assert-count 8 t:IBUF
select -assert-count 10 t:OBUF
select -assert-none t:LUT1 t:LUT2 t:LUT4 t:IBUF t:OBUF %% t:* %D