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https://github.com/YosysHQ/yosys
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Add some tests
Copied from Efinix. * fsm is broken * latch and tribuf are not implemented yet * memory maps to dram
This commit is contained in:
Pepijn de Vos
parent
03457ee13e
commit
83fbfe0964
10 changed files with 224 additions and 0 deletions
3
tests/arch/gowin/.gitignore
vendored
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3
tests/arch/gowin/.gitignore
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/*.log
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/*.out
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/run-test.mk
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13
tests/arch/gowin/add_sub.ys
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13
tests/arch/gowin/add_sub.ys
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read_verilog ../common/add_sub.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 8 t:ALU
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select -assert-count 8 t:OBUF
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select -assert-count 8 t:IBUF
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select -assert-count 1 t:GND
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select -assert-count 1 t:VCC
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select -assert-none t:ALU t:OBUF t:IBUF t:GND t:VCC %% t:* %D
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55
tests/arch/gowin/adffs.ys
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55
tests/arch/gowin/adffs.ys
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read_verilog ../common/adffs.v
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design -save read
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hierarchy -top adff
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proc
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equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adff # Constrain all select calls below inside the top module
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stat
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select -assert-count 1 t:DFFC
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select -assert-count 3 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:DFFC t:IBUF t:OBUF %% t:* %D
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design -load read
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hierarchy -top adffn
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proc
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equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adffn # Constrain all select calls below inside the top module
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select -assert-count 1 t:DFFC
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select -assert-count 1 t:LUT1
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select -assert-count 3 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:DFFC t:IBUF t:OBUF t:LUT1 %% t:* %D
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design -load read
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hierarchy -top dffs
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proc
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equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffs # Constrain all select calls below inside the top module
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select -assert-count 1 t:DFFS
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select -assert-count 4 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:DFFS t:IBUF t:OBUF %% t:* %D
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design -load read
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hierarchy -top ndffnr
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proc
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equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd ndffnr # Constrain all select calls below inside the top module
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select -assert-count 1 t:DFFNR
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select -assert-count 1 t:LUT1
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select -assert-count 4 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:DFFNR t:IBUF t:OBUF t:LUT1 %% t:* %D
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15
tests/arch/gowin/counter.ys
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15
tests/arch/gowin/counter.ys
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read_verilog ../common/counter.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 8 t:DFFC
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select -assert-count 8 t:ALU
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select -assert-count 1 t:GND
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select -assert-count 1 t:VCC
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select -assert-count 2 t:IBUF
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select -assert-count 8 t:OBUF
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select -assert-none t:DFFC t:ALU t:GND t:VCC t:IBUF t:OBUF %% t:* %D
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25
tests/arch/gowin/dffs.ys
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25
tests/arch/gowin/dffs.ys
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read_verilog ../common/dffs.v
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design -save read
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hierarchy -top dff
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proc
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dff # Constrain all select calls below inside the top module
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select -assert-count 1 t:DFF
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select -assert-count 2 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:DFF t:IBUF t:OBUF %% t:* %D
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design -load read
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hierarchy -top dffe
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proc
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffe # Constrain all select calls below inside the top module
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select -assert-count 1 t:DFFE
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select -assert-count 3 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:DFFE t:IBUF t:OBUF %% t:* %D
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13
tests/arch/gowin/logic.ys
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13
tests/arch/gowin/logic.ys
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read_verilog ../common/logic.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT1
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select -assert-count 6 t:LUT2
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select -assert-count 2 t:LUT4
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select -assert-count 8 t:IBUF
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select -assert-count 10 t:OBUF
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select -assert-none t:LUT1 t:LUT2 t:LUT4 t:IBUF t:OBUF %% t:* %D
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18
tests/arch/gowin/memory.ys
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18
tests/arch/gowin/memory.ys
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read_verilog ../common/memory.v
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hierarchy -top top
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proc
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memory -nomap
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equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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#ERROR: Called with -verify and proof did fail!
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#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
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sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd top
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select -assert-count 8 t:RAM16S4
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# other logic present that is not simple
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#select -assert-none t:RAM16S4 %% t:* %D
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50
tests/arch/gowin/mux.ys
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50
tests/arch/gowin/mux.ys
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read_verilog ../common/mux.v
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design -save read
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hierarchy -top mux2
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proc
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux2 # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT3
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select -assert-count 3 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:LUT3 t:IBUF t:OBUF %% t:* %D
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design -load read
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hierarchy -top mux4
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proc
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux4 # Constrain all select calls below inside the top module
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select -assert-count 2 t:LUT4
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select -assert-count 6 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D
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design -load read
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hierarchy -top mux8
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proc
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux8 # Constrain all select calls below inside the top module
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select -assert-count 5 t:LUT4
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select -assert-count 11 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D
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design -load read
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hierarchy -top mux16
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proc
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux16 # Constrain all select calls below inside the top module
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select -assert-count 9 t:LUT4
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select -assert-count 3 t:LUT3
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select -assert-count 20 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:LUT4 t:LUT3 t:IBUF t:OBUF %% t:* %D
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20
tests/arch/gowin/run-test.sh
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20
tests/arch/gowin/run-test.sh
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#!/usr/bin/env bash
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set -e
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{
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echo "all::"
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for x in *.ys; do
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echo "all:: run-$x"
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echo "run-$x:"
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echo " @echo 'Running $x..'"
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echo " @../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
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done
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for s in *.sh; do
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if [ "$s" != "run-test.sh" ]; then
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echo "all:: run-$s"
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echo "run-$s:"
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echo " @echo 'Running $s..'"
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echo " @bash $s"
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fi
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done
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} > run-test.mk
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exec ${MAKE:-make} -f run-test.mk
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12
tests/arch/gowin/shifter.ys
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12
tests/arch/gowin/shifter.ys
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read_verilog ../common/shifter.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 8 t:DFF
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select -assert-count 2 t:IBUF
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select -assert-count 8 t:OBUF
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select -assert-none t:DFF t:IBUF t:OBUF %% t:* %D
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