mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-30 19:22:31 +00:00
Code Activity

opt_merge to discard \init of '$' cells with 'Q' port when merging

Browse source
This commit is contained in:
Eddie Hung 2019-12-13 10:26:37 -08:00
parent d86d073ad6
commit 83d36394f8
1 changed files with 11 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

11
passes/opt/opt_merge.cc
View file

@ -323,6 +323,17 @@ struct OptMergeWorker
log_signal(it.second), log_signal(other_sig));
module->connect(RTLIL::SigSig(it.second, other_sig));
assign_map.add(it.second, other_sig);
if (cell->type.begins_with("$") && it.first == ID(Q)) {
for (auto c : it.second.chunks()) {
auto jt = c.wire->attributes.find(ID(init));
if (jt == c.wire->attributes.end())
continue;
for (int i = c.offset; i < c.offset + c.width; i++)
jt->second[i] = State::Sx;
}
dff_init_map.add(it.second, Const(State::Sx, GetSize(it.second)));
}
}
}
log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());