3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-30 16:03:17 +00:00

intel_alm: ABC9 sequential optimisations

This commit is contained in:
Dan Ravensloft 2020-05-23 12:52:13 +01:00 committed by Marcelina Kościelnicka
parent a9b61080a4
commit 83cde2d02b
7 changed files with 149 additions and 19 deletions

View file

@ -0,0 +1,11 @@
// After performing sequential synthesis, map the synchronous flops back to
// standard MISTRAL_FF flops.
module MISTRAL_FF_SYNCONLY(
input DATAIN, CLK, ENA, SCLR, SLOAD, SDATA,
output reg Q
);
MISTRAL_FF _TECHMAP_REPLACE_ (.DATAIN(DATAIN), .CLK(CLK), .ACLR(1'b1), .ENA(ENA), .SCLR(SCLR), .SLOAD(SLOAD), .SDATA(SDATA), .Q(Q));
endmodule