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verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections

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- AST_CONCAT and AST_TO_UNSIGNED are always unsigned, but may generate
  RTLIL that exclusively reference a signed wire.
- AST_CONCAT may also contain a memory write.
This commit is contained in:
Zachary Snow 2024-02-11 13:28:14 -05:00 • committed by Emil J. Tywoniak
parent 8f00c1824f
commit 83cd19678e
6 changed files with 72 additions and 9 deletions
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6
frontends/ast/simplify.cc
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@ -1367,6 +1367,12 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
else if (contains_unbased_unsized(value.get()))
// unbased unsized literals extend to width of the context
lookup_suggested = true;
else if (value->type == AST_TO_UNSIGNED)
// inner expression may be signed by default
lookup_suggested = true;
else if (value->type == AST_CONCAT && value->children.size() == 1)
// concat of a single expression is equivalent to $unsigned
lookup_suggested = true;
}
}