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Fixed const folding in corner cases with parameters
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parent
90300cbacc
commit
83a8b8b5ca
2 changed files with 27 additions and 14 deletions
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@ -199,6 +199,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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case AST_PARAMETER:
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case AST_LOCALPARAM:
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while (children[0]->simplify(false, false, false, stage, -1, false) == true) { }
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children[0]->detectSignWidth(width_hint, sign_hint);
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if (children.size() > 1) {
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assert(children[1]->type == AST_RANGE);
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@ -309,6 +310,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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bool sign_hint_here = sign_hint;
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if (i == 0 && type == AST_REPLICATE)
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const_fold_here = true;
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if (type == AST_PARAMETER || type == AST_LOCALPARAM)
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const_fold_here = true;
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if (i == 0 && (type == AST_ASSIGN || type == AST_ASSIGN_EQ || type == AST_ASSIGN_LE))
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in_lvalue_here = true;
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if (type == AST_BLOCK) {
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@ -375,7 +378,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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// resolve constant prefixes
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if (type == AST_PREFIX) {
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if (children[0]->type != AST_CONSTANT) {
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dumpAst(NULL, "> ");
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// dumpAst(NULL, "> ");
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log_error("Index in generate block prefix syntax at %s:%d is not constant!\n", filename.c_str(), linenum);
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}
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assert(children[1]->type == AST_IDENTIFIER);
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@ -593,8 +596,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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AstNode *buf = children[0]->clone();
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while (buf->simplify(true, false, false, stage, width_hint, sign_hint)) { }
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if (buf->type != AST_CONSTANT) {
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for (auto f : log_files)
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dumpAst(f, "verilog-ast> ");
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// for (auto f : log_files)
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// dumpAst(f, "verilog-ast> ");
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log_error("Condition for generate if at %s:%d is not constant!\n", filename.c_str(), linenum);
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}
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if (buf->integer != 0) {
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@ -954,16 +957,16 @@ skip_dynamic_range_lvalue_expansion:;
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{
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case AST_IDENTIFIER:
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if (current_scope.count(str) > 0 && (current_scope[str]->type == AST_PARAMETER || current_scope[str]->type == AST_LOCALPARAM)) {
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if (children.size() != 0 && children[0]->type == AST_RANGE && children[0]->range_valid) {
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if (current_scope[str]->children[0]->type == AST_CONSTANT) {
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if (current_scope[str]->children[0]->type == AST_CONSTANT) {
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if (children.size() != 0 && children[0]->type == AST_RANGE && children[0]->range_valid) {
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std::vector<RTLIL::State> data;
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for (int i = children[0]->range_right; i <= children[0]->range_left; i++)
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data.push_back(current_scope[str]->children[0]->bits[i]);
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newNode = mkconst_bits(data, false);
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}
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} else
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if (children.size() == 0)
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newNode = current_scope[str]->children[0]->clone();
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} else
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if (children.size() == 0)
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newNode = current_scope[str]->children[0]->clone();
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}
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}
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else if (at_zero && current_scope.count(str) > 0 && (current_scope[str]->type == AST_WIRE || current_scope[str]->type == AST_AUTOWIRE)) {
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newNode = mkconst_int(0, sign_hint, width_hint);
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@ -1067,7 +1070,14 @@ skip_dynamic_range_lvalue_expansion:;
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goto not_const;
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tmp_bits.insert(tmp_bits.end(), (*it)->bits.begin(), (*it)->bits.end());
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}
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newNode = mkconst_bits(tmp_bits, is_signed);
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newNode = mkconst_bits(tmp_bits, false);
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break;
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case AST_REPLICATE:
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if (children.at(0)->type != AST_CONSTANT || children.at(1)->type != AST_CONSTANT)
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goto not_const;
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for (int i = 0; i < children[0]->bitsAsConst().as_int(); i++)
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tmp_bits.insert(tmp_bits.end(), children.at(1)->bits.begin(), children.at(1)->bits.end());
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newNode = mkconst_bits(tmp_bits, false);
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break;
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default:
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not_const:
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