mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-17 04:50:29 +00:00
Code Activity

Just don't sort

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-09-18 20:56:25 +02:00
parent 9570b39519
commit 8371adf6b5
9 changed files with 2 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

2
tests/arch/xilinx/dsp_cascade.ys
View file

@ -39,7 +39,7 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad
design -load postopt
cd cascade
select -assert-count 3 t:DSP48A1
select -assert-count 5 t:FDRE # No cascade for A input
select -assert-count 10 t:FDRE # No cascade for A input
select -assert-none t:DSP48A1 t:BUFG t:FDRE %% t:* %D
# Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN
# (see above for explanation)