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Just don't sort

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This commit is contained in:
Emil J. Tywoniak 2025-09-18 20:56:25 +02:00
parent 9570b39519
commit 8371adf6b5
9 changed files with 2 additions and 10 deletions
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2
backends/verilog/verilog_backend.cc
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@ -2672,7 +2672,7 @@ struct VerilogBackend : public Backend {
Pass::call(design, "clean_zerowidth");
log_pop();
design->sort_modules();
// design->sort_modules();
*f << stringf("/* Generated by %s */\n", yosys_maybe_version());