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Fix ice40_opt for cases where a port is connected to a signal with width != 1

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-06-11 18:10:12 +02:00
parent 270c1814b5
commit 83631555dd
1 changed files with 25 additions and 9 deletions
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34
techlibs/ice40/ice40_opt.cc
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@ -26,6 +26,13 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
static SigBit get_bit_or_zero(const SigSpec &sig)
{
if (GetSize(sig) == 0)
return State::S0;
return sig[0];
}
static void run_ice40_opts(Module *module, bool unlut_mode) static void run_ice40_opts(Module *module, bool unlut_mode)
{ {
pool<SigBit> optimized_co; pool<SigBit> optimized_co;
@ -45,7 +52,11 @@ static void run_ice40_opts(Module *module, bool unlut_mode)
SigSpec non_const_inputs, replacement_output; SigSpec non_const_inputs, replacement_output;
int count_zeros = 0, count_ones = 0; int count_zeros = 0, count_ones = 0;
SigBit inbit[3] = {cell->getPort("\\I0"), cell->getPort("\\I1"), cell->getPort("\\CI")}; SigBit inbit[3] = {
get_bit_or_zero(cell->getPort("\\I0")),
get_bit_or_zero(cell->getPort("\\I1")),
get_bit_or_zero(cell->getPort("\\CI"))
};
for (int i = 0; i < 3; i++) for (int i = 0; i < 3; i++)
if (inbit[i].wire == nullptr) { if (inbit[i].wire == nullptr) {
if (inbit[i] == State::S1) if (inbit[i] == State::S1)
@ -63,8 +74,8 @@ static void run_ice40_opts(Module *module, bool unlut_mode)
replacement_output = non_const_inputs; replacement_output = non_const_inputs;
if (GetSize(replacement_output)) { if (GetSize(replacement_output)) {
optimized_co.insert(sigmap(cell->getPort("\\CO"))); optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
module->connect(cell->getPort("\\CO"), replacement_output); module->connect(cell->getPort("\\CO")[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true); module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized away SB_CARRY cell %s.%s: CO=%s\n", log("Optimized away SB_CARRY cell %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output)); log_id(module), log_id(cell), log_signal(replacement_output));
@ -78,10 +89,10 @@ static void run_ice40_opts(Module *module, bool unlut_mode)
{ {
SigSpec inbits; SigSpec inbits;
inbits.append(cell->getPort("\\I0")); inbits.append(get_bit_or_zero(cell->getPort("\\I0")));
inbits.append(cell->getPort("\\I1")); inbits.append(get_bit_or_zero(cell->getPort("\\I1")));
inbits.append(cell->getPort("\\I2")); inbits.append(get_bit_or_zero(cell->getPort("\\I2")));
inbits.append(cell->getPort("\\I3")); inbits.append(get_bit_or_zero(cell->getPort("\\I3")));
sigmap.apply(inbits); sigmap.apply(inbits);
if (unlut_mode) if (unlut_mode)
@ -104,8 +115,13 @@ static void run_ice40_opts(Module *module, bool unlut_mode)
cell->setParam("\\LUT", cell->getParam("\\LUT_INIT")); cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
cell->unsetParam("\\LUT_INIT"); cell->unsetParam("\\LUT_INIT");
cell->setPort("\\A", SigSpec({cell->getPort("\\I3"), cell->getPort("\\I2"), cell->getPort("\\I1"), cell->getPort("\\I0")})); cell->setPort("\\A", SigSpec({
cell->setPort("\\Y", cell->getPort("\\O")); get_bit_or_zero(cell->getPort("\\I3")),
get_bit_or_zero(cell->getPort("\\I2")),
get_bit_or_zero(cell->getPort("\\I1")),
get_bit_or_zero(cell->getPort("\\I0"))
}));
cell->setPort("\\Y", cell->getPort("\\O")[0]);
cell->unsetPort("\\I0"); cell->unsetPort("\\I0");
cell->unsetPort("\\I1"); cell->unsetPort("\\I1");
cell->unsetPort("\\I2"); cell->unsetPort("\\I2");