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opt_mem_feedback: Rewrite feedback path finding logic.

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Fixes #2766.
This commit is contained in:
Marcelina Kościelnicka 2021-05-24 21:21:51 +02:00
parent b706adb809
commit 835688bf80
3 changed files with 381 additions and 123 deletions
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101
tests/opt/bug2766.ys Normal file
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# Case 1.
read_verilog << EOT
module top(...);
input clk;
input sel;
input [3:0] ra;
input [3:0] wa;
input wd;
output [3:0] rd;
reg [3:0] mem[0:15];
integer i;
initial begin
for (i = 0; i < 16; i = i + 1)
mem[i] <= i;
end
assign rd = mem[ra];
always @(posedge clk) begin
mem[wa] <= {4{sel ? wd : mem[wa][0]}};
end
endmodule
EOT
hierarchy -auto-top
proc
opt_clean
design -save start
memory_map
design -save preopt
design -load start
opt_mem_feedback
memory_map
design -save postopt
equiv_opt -assert -run prepare: :
design -reset
# Case 2.
read_verilog << EOT
module top(...);
input clk;
input s1;
input s2;
input s3;
input [3:0] ra;
input [3:0] wa;
input wd;
output rd;
reg mem[0:15];
integer i;
initial begin
for (i = 0; i < 16; i = i + 1)
mem[i] <= ^i;
end
assign rd = mem[ra];
wire ta = s1 ? wd : mem[wa];
wire tb = s2 ? wd : ta;
wire tc = s3 ? tb : ta;
always @(posedge clk) begin
mem[wa] <= tc;
end
endmodule
EOT
hierarchy -auto-top
proc
opt_clean
design -save start
memory_map
design -save preopt
design -load start
opt_mem_feedback
memory_map
design -save postopt
equiv_opt -assert -run prepare: :

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tests/opt/opt_mem_feedback.ys Normal file
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# Good case: proper feedback port.
read_verilog << EOT
module top(...);
input clk;
input en;
input s;
input [3:0] ra;
output [15:0] rd;
input [3:0] wa;
input [15:0] wd;
reg [15:0] mem[0:15];
assign rd = mem[ra];
always @(posedge clk) begin
if (en) begin
mem[wa] <= {mem[wa][15:8], s ? wd[7:0] : mem[wa][7:0]};
end
end
endmodule
EOT
hierarchy -auto-top
proc
opt_clean
design -save start
memory_map
design -save preopt
design -load start
opt_mem_feedback
select -assert-count 1 t:$memrd
memory_map
design -save postopt
equiv_opt -assert -run prepare: :
design -reset
# Bad case: read port also used for other things.
read_verilog << EOT
module top(...);
input clk;
input en;
input s;
output [15:0] rd;
input [3:0] wa;
input [15:0] wd;
reg [15:0] mem[0:15];
assign rd = mem[wa];
always @(posedge clk) begin
if (en) begin
mem[wa] <= {s ? rd : wd[15:8], s ? wd[7:0] : rd};
end
end
endmodule
EOT
hierarchy -auto-top
proc
opt_clean
design -save start
memory_map
design -save preopt
design -load start
select -assert-count 1 t:$memrd
opt_mem_feedback
select -assert-count 1 t:$memrd
memory_map
design -save postopt
equiv_opt -assert -run prepare: :
design -reset
# Bad case: another user of the mux out.
read_verilog << EOT
module top(...);
input clk;
input en;
input s;
output [15:0] rd;
input [3:0] wa;
input [15:0] wd;
reg [15:0] mem[0:15];
assign rd = s ? wd : mem[wa];
always @(posedge clk) begin
if (en) begin
mem[wa] <= rd;
end
end
endmodule
EOT
hierarchy -auto-top
proc
opt_clean
design -save start
memory_map
design -save preopt
design -load start
select -assert-count 1 t:$memrd
opt_mem_feedback
select -assert-count 1 t:$memrd
memory_map
design -save postopt
equiv_opt -assert -run prepare: :