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machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph.

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This commit is contained in:
William D. Jones 2021-01-29 18:14:13 -05:00 • committed by Marcelina Kościelnicka
parent 120404bfda
commit 8348c45e4f
2 changed files with 6 additions and 6 deletions
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6
techlibs/machxo2/cells_sim.v
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@ -162,16 +162,16 @@ module FACADE_IO #(
parameter DIR = "INPUT"
) (
inout PAD,
input I, EN,
input I, T,
output O
);
generate
if (DIR == "INPUT") begin
assign O = PAD;
end else if (DIR == "OUTPUT") begin
assign PAD = EN ? I : 1'bz;
assign PAD = T ? I : 1'bz;
end else if (DIR == "BIDIR") begin
assign PAD = EN ? I : 1'bz;
assign PAD = T ? I : 1'bz;
assign O = PAD;
end else begin
ERROR_UNKNOWN_IO_MODE error();