3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 14:13:23 +00:00

Added hashing to RTLIL::SigSpec relational and equal operators

This commit is contained in:
Clifford Wolf 2014-07-23 23:58:03 +02:00
parent f368d792fb
commit 82fa356037
2 changed files with 72 additions and 18 deletions

View file

@ -505,13 +505,18 @@ struct RTLIL::SigSpecIterator {
struct RTLIL::SigSpec {
private:
int width_;
unsigned long hash_;
std::vector<RTLIL::SigChunk> chunks_; // LSB at index 0
std::vector<RTLIL::SigBit> bits_; // LSB at index 0
int width_;
void pack() const;
void unpack() const;
bool packed() const;
void hash() const;
inline bool packed() const {
return bits_.empty();
}
inline void inline_unpack() const {
if (!chunks_.empty())