mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 04:28:18 +00:00
Code Activity

Add space between -D and _ABC

Browse source
This commit is contained in:
Eddie Hung 2019-06-04 11:54:08 -07:00
parent f0e93f33cf
commit 82d41bc2f2
1 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
techlibs/xilinx/synth_xilinx.cc
View file

@ -203,9 +203,9 @@ struct SynthXilinxPass : public ScriptPass
{ {
if (check_label("begin")) { if (check_label("begin")) {
if (vpr) if (vpr)
run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); run("read_verilog -lib -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
else else
run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v"); run("read_verilog -lib -D _ABC +/xilinx/cells_sim.v");
run("read_verilog -lib +/xilinx/cells_xtra.v"); run("read_verilog -lib +/xilinx/cells_xtra.v");