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Docs: Shorten cmd:ref

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Krystine Sherwin 2024-05-03 13:16:48 +12:00
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@ -258,7 +258,7 @@ additional two parameters:
``\ARST_VALUE``
The state of ``\Q`` will be set to this value when the reset is active.
Usually these cells are generated by the :cmd:ref:`proc` pass using the
Usually these cells are generated by the `proc` pass using the
information in the designs RTLIL::Process objects.
D-type flip-flops with synchronous reset are represented by `$sdff` cells. As
@ -472,7 +472,7 @@ synthesis to succeed.
initialization conflict.
The HDL frontend models a memory using ``RTLIL::Memory`` objects and
asynchronous `$memrd_v2` and `$memwr_v2` cells. The :cmd:ref:`memory` pass
asynchronous `$memrd_v2` and `$memwr_v2` cells. The `memory` pass
(i.e. its various sub-passes) migrates `$dff` cells into the `$memrd_v2` and
`$memwr_v2` cells making them synchronous, then converts them to a single
`$mem_v2` cell and (optionally) maps this cell type to `$dff` cells for the
@ -604,14 +604,14 @@ The `$mem_v2` cell has the following ports:
This input is ``\WR_PORTS*\WIDTH`` bits wide, containing all data
signals for the write ports.
The :cmd:ref:`memory_collect` pass can be used to convert discrete
The `memory_collect` pass can be used to convert discrete
`$memrd_v2`, `$memwr_v2`, and `$meminit_v2` cells belonging to the same
memory to a single `$mem_v2` cell, whereas the :cmd:ref:`memory_unpack` pass
performs the inverse operation. The :cmd:ref:`memory_dff` pass can combine
memory to a single `$mem_v2` cell, whereas the `memory_unpack` pass
performs the inverse operation. The `memory_dff` pass can combine
asynchronous memory ports that are fed by or feeding registers into synchronous
memory ports. The :cmd:ref:`memory_bram` pass can be used to recognize
memory ports. The `memory_bram` pass can be used to recognize
`$mem_v2` cells that can be implemented with a block RAM resource on an FPGA.
The :cmd:ref:`memory_map` pass can be used to implement `$mem_v2` cells as
The `memory_map` pass can be used to implement `$mem_v2` cells as
basic logic: word-wide DFFs and address decoders.
Finite state machines