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Docs: Shorten cmd:ref
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@ -258,7 +258,7 @@ additional two parameters:
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``\ARST_VALUE``
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The state of ``\Q`` will be set to this value when the reset is active.
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Usually these cells are generated by the :cmd:ref:`proc` pass using the
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Usually these cells are generated by the `proc` pass using the
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information in the designs RTLIL::Process objects.
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D-type flip-flops with synchronous reset are represented by `$sdff` cells. As
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@ -472,7 +472,7 @@ synthesis to succeed.
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initialization conflict.
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The HDL frontend models a memory using ``RTLIL::Memory`` objects and
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asynchronous `$memrd_v2` and `$memwr_v2` cells. The :cmd:ref:`memory` pass
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asynchronous `$memrd_v2` and `$memwr_v2` cells. The `memory` pass
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(i.e. its various sub-passes) migrates `$dff` cells into the `$memrd_v2` and
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`$memwr_v2` cells making them synchronous, then converts them to a single
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`$mem_v2` cell and (optionally) maps this cell type to `$dff` cells for the
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@ -604,14 +604,14 @@ The `$mem_v2` cell has the following ports:
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This input is ``\WR_PORTS*\WIDTH`` bits wide, containing all data
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signals for the write ports.
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The :cmd:ref:`memory_collect` pass can be used to convert discrete
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The `memory_collect` pass can be used to convert discrete
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`$memrd_v2`, `$memwr_v2`, and `$meminit_v2` cells belonging to the same
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memory to a single `$mem_v2` cell, whereas the :cmd:ref:`memory_unpack` pass
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performs the inverse operation. The :cmd:ref:`memory_dff` pass can combine
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memory to a single `$mem_v2` cell, whereas the `memory_unpack` pass
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performs the inverse operation. The `memory_dff` pass can combine
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asynchronous memory ports that are fed by or feeding registers into synchronous
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memory ports. The :cmd:ref:`memory_bram` pass can be used to recognize
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memory ports. The `memory_bram` pass can be used to recognize
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`$mem_v2` cells that can be implemented with a block RAM resource on an FPGA.
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The :cmd:ref:`memory_map` pass can be used to implement `$mem_v2` cells as
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The `memory_map` pass can be used to implement `$mem_v2` cells as
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basic logic: word-wide DFFs and address decoders.
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Finite state machines
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