mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 22:23:23 +00:00
Code Activity

Docs: Shorten cmd:ref

Browse source
This commit is contained in:
Krystine Sherwin 2024-05-03 13:16:48 +12:00
parent e4ec3717bc
commit 829e02ec5b
No known key found for this signature in database
22 changed files with 296 additions and 297 deletions
Download patch file Download diff file Expand all files Collapse all files

14
docs/source/yosys_internals/formats/cell_library.rst
View file

@ -258,7 +258,7 @@ additional two parameters:
``\ARST_VALUE``
The state of ``\Q`` will be set to this value when the reset is active.
Usually these cells are generated by the :cmd:ref:`proc` pass using the
Usually these cells are generated by the `proc` pass using the
information in the designs RTLIL::Process objects.
D-type flip-flops with synchronous reset are represented by `$sdff` cells. As
@ -472,7 +472,7 @@ synthesis to succeed.
initialization conflict.
The HDL frontend models a memory using ``RTLIL::Memory`` objects and
asynchronous `$memrd_v2` and `$memwr_v2` cells. The :cmd:ref:`memory` pass
asynchronous `$memrd_v2` and `$memwr_v2` cells. The `memory` pass
(i.e. its various sub-passes) migrates `$dff` cells into the `$memrd_v2` and
`$memwr_v2` cells making them synchronous, then converts them to a single
`$mem_v2` cell and (optionally) maps this cell type to `$dff` cells for the
@ -604,14 +604,14 @@ The `$mem_v2` cell has the following ports:
This input is ``\WR_PORTS*\WIDTH`` bits wide, containing all data
signals for the write ports.
The :cmd:ref:`memory_collect` pass can be used to convert discrete
The `memory_collect` pass can be used to convert discrete
`$memrd_v2`, `$memwr_v2`, and `$meminit_v2` cells belonging to the same
memory to a single `$mem_v2` cell, whereas the :cmd:ref:`memory_unpack` pass
performs the inverse operation. The :cmd:ref:`memory_dff` pass can combine
memory to a single `$mem_v2` cell, whereas the `memory_unpack` pass
performs the inverse operation. The `memory_dff` pass can combine
asynchronous memory ports that are fed by or feeding registers into synchronous
memory ports. The :cmd:ref:`memory_bram` pass can be used to recognize
memory ports. The `memory_bram` pass can be used to recognize
`$mem_v2` cells that can be implemented with a block RAM resource on an FPGA.
The :cmd:ref:`memory_map` pass can be used to implement `$mem_v2` cells as
The `memory_map` pass can be used to implement `$mem_v2` cells as
basic logic: word-wide DFFs and address decoders.
Finite state machines

4
docs/source/yosys_internals/formats/rtlil_rep.rst
View file

@ -76,7 +76,7 @@ This has three advantages:
- Second, the information about which identifiers were originally provided by
the user is always available which can help guide some optimizations. For
example, :cmd:ref:`opt_clean` tries to preserve signals with a user-provided
example, `opt_clean` tries to preserve signals with a user-provided
name but doesn't hesitate to delete signals that have auto-generated names
when they just duplicate other signals. Note that this can be overridden
with the ``-purge`` option to also delete internal nets with user-provided
@ -320,7 +320,7 @@ trees before further processing them.
One of the first actions performed on a design in RTLIL representation in most
synthesis scripts is identifying asynchronous resets. This is usually done using
the :cmd:ref:`proc_arst` pass. This pass transforms the above example to the
the `proc_arst` pass. This pass transforms the above example to the
following ``RTLIL::Process``:
.. code:: RTLIL