mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-10 16:13:26 +00:00
Code Activity

Docs: Shorten cmd:ref

Browse source
This commit is contained in:
Krystine Sherwin 2024-05-03 13:16:48 +12:00
parent e4ec3717bc
commit 829e02ec5b
No known key found for this signature in database
22 changed files with 296 additions and 297 deletions
Download patch file Download diff file Expand all files Collapse all files

20
docs/source/using_yosys/synthesis/abc.rst
View file

@ -10,11 +10,11 @@ fine-grained optimisation and LUT mapping.
Yosys has two different commands, which both use this logic toolbox, but use it
in different ways.
The :cmd:ref:`abc` pass can be used for both ASIC (e.g. :yoscrypt:`abc
The `abc` pass can be used for both ASIC (e.g. :yoscrypt:`abc
-liberty`) and FPGA (:yoscrypt:`abc -lut`) mapping, but this page will focus on
FPGA mapping.
The :cmd:ref:`abc9` pass generally provides superior mapping quality due to
The `abc9` pass generally provides superior mapping quality due to
being aware of combination boxes and DFF and LUT timings, giving it a more
global view of the mapping problem.
@ -23,7 +23,7 @@ global view of the mapping problem.
ABC: the unit delay model, simple and efficient
-----------------------------------------------
The :cmd:ref:`abc` pass uses a highly simplified view of an FPGA:
The `abc` pass uses a highly simplified view of an FPGA:
- An FPGA is made up of a network of inputs that connect through LUTs to a
network of outputs. These inputs may actually be I/O pins, D flip-flops,
@ -126,7 +126,7 @@ guide to the syntax:
By convention, all delays in ``specify`` blocks are in integer picoseconds.
Files containing ``specify`` blocks should be read with the ``-specify`` option
to :cmd:ref:`read_verilog` so that they aren't skipped.
to `read_verilog` so that they aren't skipped.
LUTs
^^^^
@ -145,9 +145,9 @@ DFFs
DFFs should be annotated with an ``(* abc9_flop *)`` attribute, however ABC9 has
some specific requirements for this to be valid: - the DFF must initialise to
zero (consider using :cmd:ref:`dfflegalize` to ensure this). - the DFF cannot
have any asynchronous resets/sets (see the simplification idiom and the Boxes
section for what to do here).
zero (consider using `dfflegalize` to ensure this). - the DFF cannot have any
asynchronous resets/sets (see the simplification idiom and the Boxes section for
what to do here).
It is worth noting that in pure ``abc9`` mode, only the setup and arrival times
are passed to ABC9 (specifically, they are modelled as buffers with the given
@ -158,9 +158,9 @@ Some vendors have universal DFF models which include async sets/resets even when
they're unused. Therefore *the simplification idiom* exists to handle this: by
using a ``techmap`` file to discover flops which have a constant driver to those
asynchronous controls, they can be mapped into an intermediate, simplified flop
which qualifies as an ``(* abc9_flop *)``, ran through :cmd:ref:`abc9`, and then
mapped back to the original flop. This is used in :cmd:ref:`synth_intel_alm` and
:cmd:ref:`synth_quicklogic` for the PolarPro3.
which qualifies as an ``(* abc9_flop *)``, ran through `abc9`, and then mapped
back to the original flop. This is used in `synth_intel_alm` and
`synth_quicklogic` for the PolarPro3.
DFFs are usually specified to have setup constraints against the clock on the
input signals, and an arrival time for the ``Q`` output.