block ram mapping for standard modes

techlibs/nanoxplore/brams.txt

@@ -1,26 +1,46 @@
 ram block $__NX_RAM_ {
-	abits 13;
+	option "STD_MODE" "NOECC_48kx1" {
-	widths 1 2 4 9 per_port;
+		# only 32k used
+		abits 15;
+		widths 1 global;
+	}
+	option "STD_MODE" "NOECC_24kx2" {
+		# only 16k used
+		abits 14;
+		widths 2 global;
+	}
+	option "STD_MODE" "NOECC_16kx3" {
+		abits 14;
+		widths 3 global;
+	}
+	option "STD_MODE" "NOECC_12kx4" {
+		# only 8k used
+		abits 13;
+		widths 4 global;
+	}
+	option "STD_MODE" "NOECC_8kx6" {
+		abits 13;
+		widths 6 global;
+	}
+	option "STD_MODE" "NOECC_6kx8" {
+		# only 4k used
+		abits 12;
+		widths 8 global;
+	}
+	option "STD_MODE" "NOECC_4kx12" {
+		abits 12;
+		widths 12 global;
+	}
+	option "STD_MODE" "NOECC_2kx24" {
+		abits 11;
+		widths 24 global;
+	}
 	cost 64;
 	init no_undef;
 	port srsw "A" "B" {
 		clock anyedge;
 		clken;
-		portoption "WRITEMODE" "NORMAL" {
+		rdwr no_change;
-			rdwr no_change;
+		rdinit none;
-		}
-		portoption "WRITEMODE" "WRITETHROUGH" {
-			rdwr new;
-		}
-		portoption "WRITEMODE" "READBEFOREWRITE" {
-			rdwr old;
-		}
-		option "RESETMODE" "SYNC" {
-			rdsrst zero ungated block_wr;
-		}
-		option "RESETMODE" "ASYNC" {
-			rdarst zero;
-		}
-		rdinit zero;
 	}
 }

techlibs/nanoxplore/brams_map.v

@@ -1,43 +1,93 @@
 module $__NX_RAM_ (...);
 
 parameter INIT = 0;
-parameter OPTION_RESETMODE = "SYNC";
+parameter OPTION_STD_MODE = "";
 
-parameter PORT_A_WIDTH = 9;
+parameter WIDTH = 24;
 parameter PORT_A_CLK_POL = 1;
-parameter PORT_A_OPTION_WRITEMODE = "NORMAL";
 
 input PORT_A_CLK;
 input PORT_A_CLK_EN;
 input PORT_A_WR_EN;
-input PORT_A_RD_SRST;
+input [15:0] PORT_A_ADDR;
-input PORT_A_RD_ARST;
+input [WIDTH-1:0] PORT_A_WR_DATA;
-input [12:0] PORT_A_ADDR;
+wire [24-1:0] A_DATA;
-input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
+output [WIDTH-1:0] PORT_A_RD_DATA;
-output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
 
-parameter PORT_B_WIDTH = 9;
 parameter PORT_B_CLK_POL = 1;
-parameter PORT_B_OPTION_WRITEMODE = "NORMAL";
 
 input PORT_B_CLK;
 input PORT_B_CLK_EN;
 input PORT_B_WR_EN;
-input PORT_B_RD_SRST;
+input [15:0] PORT_B_ADDR;
-input PORT_B_RD_ARST;
+input [WIDTH-1:0] PORT_B_WR_DATA;
-input [12:0] PORT_B_ADDR;
+wire [24-1:0] B_DATA;
-input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
+output [WIDTH-1:0] PORT_B_RD_DATA;
-output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
+
+generate
+    if (OPTION_STD_MODE == "NOECC_48kx1") begin
+        assign A_DATA = {24{PORT_A_WR_DATA[WIDTH-1:0]}};
+        assign B_DATA = {24{PORT_B_WR_DATA[WIDTH-1:0]}};
+    end
+    else if (OPTION_STD_MODE == "NOECC_24kx2") begin
+        assign A_DATA = {12{PORT_A_WR_DATA[WIDTH-1:0]}};
+        assign B_DATA = {12{PORT_B_WR_DATA[WIDTH-1:0]}};
+    end
+    else if (OPTION_STD_MODE == "NOECC_16kx3") begin
+        assign A_DATA = {8{PORT_A_WR_DATA[WIDTH-1:0]}};
+        assign B_DATA = {8{PORT_B_WR_DATA[WIDTH-1:0]}};
+    end
+    else if (OPTION_STD_MODE == "NOECC_12kx4") begin
+        assign A_DATA = {6{PORT_A_WR_DATA[WIDTH-1:0]}};
+        assign B_DATA = {6{PORT_B_WR_DATA[WIDTH-1:0]}};
+    end
+    else if (OPTION_STD_MODE == "NOECC_8kx6") begin
+        assign A_DATA = {4{PORT_A_WR_DATA[WIDTH-1:0]}};
+        assign B_DATA = {4{PORT_B_WR_DATA[WIDTH-1:0]}};
+    end
+    else if (OPTION_STD_MODE == "NOECC_6kx8") begin
+        assign A_DATA = {3{PORT_A_WR_DATA[WIDTH-1:0]}};
+        assign B_DATA = {3{PORT_B_WR_DATA[WIDTH-1:0]}};
+    end
+    else if (OPTION_STD_MODE == "NOECC_4kx12") begin
+        assign A_DATA = {2{PORT_A_WR_DATA[WIDTH-1:0]}};
+        assign B_DATA = {2{PORT_B_WR_DATA[WIDTH-1:0]}};
+    end
+    else if (OPTION_STD_MODE == "NOECC_2kx24") begin
+        assign A_DATA = PORT_A_WR_DATA;
+        assign B_DATA = PORT_B_WR_DATA;
+    end
+endgenerate
 
 NX_RAM_WRAP #(
+    .std_mode(OPTION_STD_MODE),
+    .mcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1),
+    .mckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1),
 ) _TECHMAP_REPLACE_ (
     .ACK(PORT_A_CLK),
+    //.ACKS(PORT_A_CLK),
+    //.ACKD(), // Not used in Non-ECC modes
+    //.ACKR(),
+    //.AR(),
+    //.ACOR(),
+    //.AERR(),
+    .ACS(PORT_A_CLK_EN),
+    .AWE(PORT_A_WR_EN),
+
     .AA(PORT_A_ADDR),
-    .AI(PORT_A_WR_DATA),
+    .AI(A_DATA),
     .AO(PORT_A_RD_DATA),
 
     .BCK(PORT_B_CLK),
-    .BA(PORT_B_ADDR),
+    //.BCKC(PORT_B_CLK),
+    //.BCKD(), // Not used in Non-ECC modes
+    //.BCKR()
+    //.BR(),
+    //.BCOR(),
+    //.BERR(),
+    .BCS(PORT_B_CLK_EN),
+    .BWE(PORT_B_WR_EN),
+    .BA(B_DATA),
     .BI(PORT_B_WR_DATA),
     .BO(PORT_B_RD_DATA)
 );

techlibs/nanoxplore/cells_bb.v

@@ -255,10 +255,10 @@ module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4,
     parameter pipe_ob = 1'b0;
     parameter raw_config0 = 4'b0000;
     parameter raw_config1 = 16'b0000000000000000;
-    parameter raw_l_enable = 1'b0;
+    //parameter raw_l_enable = 1'b0;
-    parameter raw_l_extend = 4'b0000;
+    //parameter raw_l_extend = 4'b0000;
-    parameter raw_u_enable = 1'b0;
+    //parameter raw_u_enable = 1'b0;
-    parameter raw_u_extend = 8'b00000000;
+    //parameter raw_u_extend = 8'b00000000;
     parameter std_mode = "";
 endmodule