3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-08-05 05:43:37 +00:00

dfflibmap: error on wide registers in design

This commit is contained in:
Emil J. Tywoniak 2026-07-27 22:24:28 +02:00
parent db2b3a22e9
commit 82914a0204
2 changed files with 11 additions and 0 deletions

View file

@ -0,0 +1,5 @@
read_verilog ../sim/dff.v
proc
logger -expect error "not supported" 1
dfflibmap -liberty dfflibmap.lib
logger -check-expected