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dfflibmap: error on wide registers in design
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5
tests/techmap/dfflibmap_wide.ys
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5
tests/techmap/dfflibmap_wide.ys
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@ -0,0 +1,5 @@
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read_verilog ../sim/dff.v
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proc
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logger -expect error "not supported" 1
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dfflibmap -liberty dfflibmap.lib
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logger -check-expected
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