Merge pull request #5152 from garytwong/unique-if

verilog: implement SystemVerilog unique/unique0/priority if semantics.

docs/source/yosys_internals/verilog.rst

@@ -377,7 +377,7 @@ from SystemVerilog:
 - Assignments within expressions are supported.
 
 - The ``unique``, ``unique0``, and ``priority`` SystemVerilog keywords are
-  accepted on ``if`` and ``case`` conditionals.  (Those keywords are currently
-  handled in the same way as their equivalent ``full_case`` and
-  ``parallel_case`` attributes on ``case`` statements, and checked
-  for syntactic validity but otherwise ignored on ``if`` statements.)
+  supported on ``if`` and ``case`` conditionals.  (The Verilog frontend
+  will process conditionals using these keywords by annotating their
+  representation with the appropriate ``full_case`` and/or ``parallel_case``
+  attributes, which are described above.)