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Merge pull request #5152 from garytwong/unique-if

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verilog: implement SystemVerilog unique/unique0/priority if semantics.
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KrystalDelusion 2025-06-13 09:56:53 +12:00 • committed by GitHub
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docs/source/yosys_internals/verilog.rst
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@ -377,7 +377,7 @@ from SystemVerilog:
- Assignments within expressions are supported.
- The ``unique``, ``unique0``, and ``priority`` SystemVerilog keywords are
accepted on ``if`` and ``case`` conditionals. (Those keywords are currently
handled in the same way as their equivalent ``full_case`` and
``parallel_case`` attributes on ``case`` statements, and checked
for syntactic validity but otherwise ignored on ``if`` statements.)
supported on ``if`` and ``case`` conditionals. (The Verilog frontend
will process conditionals using these keywords by annotating their
representation with the appropriate ``full_case`` and/or ``parallel_case``
attributes, which are described above.)