Merge pull request #5152 from garytwong/unique-if

verilog: implement SystemVerilog unique/unique0/priority if semantics.

docs/source/cell/word_mux.rst

@@ -24,8 +24,8 @@ are zero, the value from ``A`` input is sent to the output. If the :math:`n`\
 'th bit from ``S`` is set, the value :math:`n`\ 'th ``WIDTH`` bits wide slice of
 the ``B`` input is sent to the output. When more than one bit from ``S`` is set
 the output is undefined. Cells of this type are used to model "parallel cases"
-(defined by using the ``parallel_case`` attribute or detected by an
-optimization).
+(defined by using the ``parallel_case`` attribute, the ``unique`` or ``unique0``
+SystemVerilog keywords, or detected by an optimization).
 
 The `$tribuf` cell is used to implement tristate logic. Cells of this type have
 a ``WIDTH`` parameter and inputs ``A`` and ``EN`` and an output ``Y``. The ``A``

docs/source/yosys_internals/verilog.rst

@@ -377,7 +377,7 @@ from SystemVerilog:
 - Assignments within expressions are supported.
 
 - The ``unique``, ``unique0``, and ``priority`` SystemVerilog keywords are
-  accepted on ``if`` and ``case`` conditionals.  (Those keywords are currently
-  handled in the same way as their equivalent ``full_case`` and
-  ``parallel_case`` attributes on ``case`` statements, and checked
-  for syntactic validity but otherwise ignored on ``if`` statements.)
+  supported on ``if`` and ``case`` conditionals.  (The Verilog frontend
+  will process conditionals using these keywords by annotating their
+  representation with the appropriate ``full_case`` and/or ``parallel_case``
+  attributes, which are described above.)