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ALU sim tweaks

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This commit is contained in:
Pepijn de Vos 2019-10-24 13:39:43 +02:00
parent 83fbfe0964
commit 8226f2db0b
2 changed files with 13 additions and 13 deletions
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4
tests/arch/gowin/mux.ys
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@ -42,8 +42,8 @@ proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-count 9 t:LUT4
select -assert-count 3 t:LUT3
select -assert-count 10 t:LUT4
select -assert-count 1 t:LUT3
select -assert-count 20 t:IBUF
select -assert-count 1 t:OBUF